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It’s performance evaluation season at work right now so my plans are delayed a week or two, but the latest Arcflash board design is looking good and working for me and Ian, so I’m going to build a little batch from the components I have here (I think I have enough for 10 boards). If those all work f...

I think Ramtop's point is that the Xilinx programmer won't supply power to the CPLD; the CPLD has to be powered already for JTAG to work. sP1d3r, can you check voltages with a multimeter and make sure that the 3.3V pin on the EXTPWR header is showing up as 3.3V? That's the big one. Maybe I could mak...

Looks like not much battery damage aside from the PCF8583, at least

I'm a bit late, but I like my Siglent SDS1104X-E (updated to 200MHz). Very much worth the $543.91 it cost me in California.

If you don't have a scope, a cheap-ish logic analyzer is the next best thing... do all the things that Ian suggested, then check each ROM address line in turn to make sure you see a square wave. You can even get part of the way with just a multimeter on the DC voltage setting; a 0-5V square wave wil...

Tonight's project is to try to figure out why I'm getting serial port issues on my v3 board: serial reception just stops working halfway through a ROM upload sometimes, and the upload script times out, then if I connect to the Arcflash manually (screen /dev/tty.usbmodem* on my Mac), I see the connec...

The reason for weird things happening with the near connector is that it maps into ROM positions 4 and 5, which aren't used on a Plus 1. The middle connector is ROM 2/3, and the far connector is ROM 0/1.

It's interesting output in that there's nothing to the right of any of the colons so I'm not really sure it's right. This is RISC OS 3.71 (ARM7500FE ofc). I think that just means that the tests passed for that memory block. Here's what I got the last time I ran the self-test on my A7000; the three ...

That's very tempting! I'm going to grab one too, although I fear this will end up as one of those things I buy and only use once or twice, and never do it justice

Maybe something to try running RISC-V Linux on?

Hold on .... should the connector be at the bottom of the board???? That might explain why mine doesn’t work. I have the connector at the top.... Yep, it goes on the bottom :/ Time for me to document some of this on GitHub, I think... looks like this has bitten both of you now (and I see sP1d3r has...

Hang on, that is the same as the connector that I bought. That one can only be attached to the top of the board because of the placement of the slot. Don't get that one unless someone know how to remove and re-arrange the contacts and separators in a connector like that! For the benefit of anyone g...

Progress, progress... hooked a POST Box r2 to the bad A3000 with Arcflash v3, manually selected RISC OS 3.11 with "Y22" on the Arcflash serial port (Y = select bank; 2 = select bank @ 2MB; 2 = select bank size 2MB) and it output a nice self-test: SELFTEST R1.47 ROM : M Size : M Size 0200.0...

Here's the Minus One I programmed a few days back with the Leonardo; it's looking good, running Elite on this Elk here

Hi everyone, I just joined the *. to say thanks for breathing life into my old Electron! Hooray! Glad my little project came of use :) I got the blank PCB, along with an "Electron" right angle edge connector off of e-bay, and some other card connectors and the CPLDs from some more reputab...

I found a solution to my previous post by downloading the zipped resource folders from Github and extracting the contents to the correct folder in my desktop. Looks like I had specified all the submodules with git@github.com urls, so you needed a GH login to make anything work! I've changed them to...

Ah! I missed a step in the instructions. Run this to get all the missing bits:

git submodule update --init

The problem with components like the smd resistor networks and smd chips with 0.5mm pin spacing is that in industry these parts are placed by machine on solder paste that's printed onto the pcb pads, before the reflow oven. Without a solder paste printer and a pick and place machine these parts are...

Here's sP1d3r's original post over in the other thread , to bring things together: I'm trying to program an assembled Minus One interface that I've got, a Minus One is an interface for an Elk that has 3 cartridge slots, one of myelin's github projects, url: https://github.com/google/myelin-acorn-ele...

BTW I found my Leonardo board, so when I get a minute I’ll see about verifying that I can program the Minus One CPLD with it, and post instructions.

Does TDO connect to TDI and vice-versa? If you're connecting a JTAG box like the Xilinx one to a target board, connect everything straight across. When you have a single target, the connections look like this: +-------------+ +-------------+ | VCC --- VCC | | Xilinx GND --- GND | | USB JTAG TCK ---...

rhalkyard wrote: ↑

Wed Jan 20, 2021 3:47 pm

While I live in the US these days, I'm originally from New Zealand, and have great nostalgia for the Beebs and Archimedes machines that I grew up using in school.

Yay! Another one!

Where in the US are you?

Oh you're way ahead. Excellent. I've not sorted out the plan for soldering the BGAs yet and DHL lost my stencil -- just arrived today and Xilinx programmer still en-route. :) I've now kitted to make up all 5 boards (was just planning on a couple originally) and plan to test on A3000, A300 and A400 ...

Well, maybe my soldering skills aren't that good after all. The board does not work correctly. Without any cartridges the Elk start fine and works as normal. After placing a cartridge into a slot the screen is corrupt and the Elk behaves very bad. Sometimes it doesn't hang after a reset but pressin...

I went to the Digilent website for a look at a Jtag-HS2 and there's not much similarity, so rather than try to program the device detected by Boundary Scan, I looked for some help files and found the page in the picture. If you plug it in (making sure to get the pinout right; you'll need to use the...

Found some time today so I won’t be too far behind you testing v3! (Pictured before cleaning up all the solder bridges after reflow.)

One possibility: The pinout on the programming connector is unconventional...I have a doc about this in the repo somewhere. It’s the Altera jtag pinout rather than the Xilinx one :) Here's the full explanation: https://github.com/google/myelin-acorn-electron-hardware/blob/master/notes/pld_programmin...

Yeah, the 0.1" header on Arcflash isn't a standard Cortex header, I'm afraid. (The one on the POST Box is.) I've just pushed an update to the BOM to clarify that the four decoupling caps on the bottom layer are optional; you can get away with just populating the top layer: https://github.com/go...

Let's go! =D> Looks like you're going to have a v3 board built before me! I just had a quick check to make sure all my recent changes have been checked in to GitHub, and it looks like they are (aside from a tweak to the serial console to allow specifying rom banks 0-e rather than 0-9, which isn't t...

Did I forget to drop a link to the guide in the letter that was in the box? It's in the letter - but it was inaccessible. I did "request access" twice. :lol: ... and they're in my gmail spam folder :roll: I guessed, and as it was showing as a circuit playground, I just googled for a circu...

Ok, I'll try and rebuild the firmware (on Win/Linux, whatever). This may be described in your guide but I still don't have access to that (hint hint again ;) ) Firmware build & flash Is my bread & butter anyway. Did I forget to drop a link to the guide in the letter that was in the box? It'...

Okay! By process of elimination, it appears to be the debug settings I used when compiling the firmware. Commenting out the DEBUG and DEBUG_FLAGS lines from firmware/Makefile appears to completely prevent the hanging serial port issue on the two boards (r1/#1 and r2/#5) I've tested it on :) Time to ...