Acorn Electron - Shadow Ram

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W_oo_d
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Acorn Electron - Shadow Ram

Postby W_oo_d » Sat Dec 03, 2016 3:38 pm

Hi :)

How can I directly access the screen memory when using the Slogger Ram board?

Thx

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danielj
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Re: Acorn Electron - Shadow Ram

Postby danielj » Sat Dec 03, 2016 4:02 pm

So, my reading of the manual is that you can only access a byte at a time using a new OS call at &FBFD:

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NEW OPERATING SYSTEM CALL   &FBFD
12K of memory or more, depending on screen mode, is free for use by the user. This memory can only be accessed vim a JUMP address at location FBFD in the new MOS.

Entry Parameters
X,Y contain 16 bit address, X=low byte, Y=high byte
A = Byte to write to memory or byte read from memory
Overflow flag.. .Clear = Read             Set=Write
On exit X and Y registers are preserved. A is preserved on write

Example to read Electron RAM location:

LDX         - address LSB
LDY         - address MSB
CLV         - clear overflow for read
JSR &FBFD


You'd have to disassemble the MRB MOS to see exactly what it's up to - I suspect you have to flip a bit which swaps the bottom 32k. You'd be able to mess with it on a grander scale you were running from a ROM but from RAM I'm guessing you're stuck with a byte at a time.

d.

SarahWalker
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Re: Acorn Electron - Shadow Ram

Postby SarahWalker » Sat Dec 03, 2016 4:12 pm

Looking through the Elkulator source, it looks like &FC7F is the MRB control register. Only the top bit seems to be used, and the mapping looks like :

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FC7F=&80 :
0000-2fff = normal RAM
3000-7fff = normal RAM

FC7F=&00, MRB in 'turbo' mode :
0000-2fff = shadow RAM
3000-7fff = normal RAM

FC7F=&00, MRB in 'shadow' mode :
0000-2fff = shadow RAM
3000-7fff = shadow RAM, EXCEPT when accessed by code at &C000-&DFFF (OS VDU drivers)

As in shadow mode this will remap all RAM, this will be tricky to use in code being executed in RAM - you'll have to use &FBFD to ensure that your code exists in both normal and shadow banks, otherwise you'll crash pretty quickly.

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W_oo_d
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Re: Acorn Electron - Shadow Ram

Postby W_oo_d » Sat Dec 03, 2016 4:45 pm

Thank you for clarifying the issue. I was hoping that there was another way than using &FBFD :)

I am going to play with the &FC7F banking system and see what I can do.

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jgharston
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Re: Acorn Electron - Shadow Ram

Postby jgharston » Sat Dec 03, 2016 9:42 pm

Adapting the BBC/Master vram paging routine and examining the shadow RAM support code, it looks like the following routine would be the Electron equivalent:

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 \ Electron screen selection routine
 \ =================================
 \ On entry, A=0 - select main memory
 \           A=1 - select video memory
 \ On exit,  A corrupted, X,Y preserved
 \
  .vramSelect
 ROR A                 :\ Move selection in bit 0 to Carry
 LDA &027F:BPL vramOk  :\ No shadow RAM present
 ROR A:STA &FC7F       :\ Move Carry A to bit 7, set paging flag
 .vramOk
 RTS

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$ bbcbasic
PDP11 BBC BASIC IV Version 0.25
(C) Copyright J.G.Harston 1989,2005-2015
>_

ThomasHarte
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Re: Acorn Electron - Shadow Ram

Postby ThomasHarte » Mon Dec 05, 2016 4:12 pm

My old memory is embarrassing me again, but I believe the MRB latches the address bus upon sync (i.e. it tracks the program counter) and determines which section of memory to show — at least in part — based on whether it is at or above D000 (or maybe E000, but probably D000). Sadly I don't recall whether this is in conjunction with or as an alternative to the paging register.

I guess that you'll find out one way or the other pretty quickly.

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jgharston
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Re: Acorn Electron - Shadow Ram

Postby jgharston » Mon Dec 05, 2016 5:53 pm

ThomasHarte wrote:My old memory is embarrassing me again, but I believe the MRB latches the address bus upon sync (i.e. it tracks the program counter) and determines which section of memory to show — at least in part — based on whether it is at or above D000 (or maybe E000, but probably D000). Sadly I don't recall whether this is in conjunction with or as an alternative to the paging register.

The MOS code suggests that code executing at &C000-&DFFF always accesses video RAM, code elsewhere accesses the RAM specified by bit 7 of &FC7F.

Code: Select all

$ bbcbasic
PDP11 BBC BASIC IV Version 0.25
(C) Copyright J.G.Harston 1989,2005-2015
>_

ThomasHarte
Posts: 327
Joined: Sat Dec 23, 2000 5:56 pm

Re: Acorn Electron - Shadow Ram

Postby ThomasHarte » Thu Dec 08, 2016 3:23 pm

jgharston wrote:
ThomasHarte wrote:My old memory is embarrassing me again, but I believe the MRB latches the address bus upon sync (i.e. it tracks the program counter) and determines which section of memory to show — at least in part — based on whether it is at or above D000 (or maybe E000, but probably D000). Sadly I don't recall whether this is in conjunction with or as an alternative to the paging register.

The MOS code suggests that code executing at &C000-&DFFF always accesses video RAM, code elsewhere accesses the RAM specified by bit 7 of &FC7F.

Yep, I found some old notes and that's exactly what I used to know. The MSB of FC7F selects entire-range RAM visibility; the exception is that operations with their first byte in C000–DFFF that address 3000–7FFF always see the ordinary built-in memory.

Possibly accurate and possibly not, I also seem to have believed that when operating in turbo mode, the 0000–2FFF turbo RAM is paged in and out via FC7F. So if the original author was happy with an extra 12kb rather than an extra 32kb, that offers slightly more conventional paging. Use a 40-column mode, put your speed-dependent routines into the extra 12kb, put at least the paging part of your code into part of the unpaged 20kb that isn't the screen.


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