Fixing a Superbrain up

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jonb
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Re: Fixing a Superbrain up

Postby jonb » Fri May 12, 2017 9:14 am

Trace time!

DS1Z_QuickPrint23.png
Y-/MREQ, C=CPU2 BUS ENA, M=D0 (ROM), B=D0 (CPU1)


The problem is, this is the ICE in Quit mode (CPU halted) yet /MREQ is still active. I can't trigger on /MREQ and capture the access cycle because it is cycling constantly. I'm not sure what it means but if I zoom right out I get this:

DS1Z_QuickPrint24.png
Y-/MREQ, C=CPU2 BUS ENA, M=D0 (ROM), B=D0 (CPU1)


Maybe the refresh signal is getting mixed in somehow?

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jonb
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Re: Fixing a Superbrain up

Postby jonb » Fri May 12, 2017 9:19 am

Hmm...

DS1Z_QuickPrint25.png
Y-/MREQ, C=CPU2 BUS ENA, M=/REFSH, B=D0 (CPU1)


Might I conclude from this that the /REFSH is interfering with /MREQ?

On the other hand:

Z80 ICE manual wrote:The ICE consists of a 6 MHz Z80 CPU, a CPLD custom logic chip, an RS-232 level translator/charge
pump chip, and a PIC microcontroller. The PIC chip communicates with the terminal through the RS-232 chip
and controls the Z80. It is capable of reading Z80 register values, loading the Z80’s registers, single-stepping
the Z80 through code, starting the Z80 running at full speed, and stopping the Z80. The CPLD chip contains
logic to allow the PIC to control the Z80 and also to inhibit the bus request and interrupt signals from reaching
the Z80. It can also prevent the Z80’s MREQ, IOREQ, RD, and WR signals from reaching the target system. In
Quit mode, these four signals are forced to their inactive state in the target system, to insure that the target
system is not using the data bus. This is necessary as the data bus is used for PIC-to-Z80 communication in this
mode.
In Go mode, the PIC chip starts up the Z80 and lets it run. In this mode, the ICE operates just like a
normal Z80 chip. In Quit mode, the Z80 has been paused, and can be used to implement the commands that
give the ICE its power. All communication with the target system’s memory takes place through the Z80. To
read data from a memory location, the PIC arranges for the Z80 to read from that location, and then hand the
data to the PIC. If the Z80 is halted, it is not fetching op codes, and cannot be controlled by the PIC chip. This
condition is detected and a message is displayed. The system must be reset to restore normal operation.


My probes are on the Z80 socket on the Superbrain board, not on the Z80 itself (mounted on the ICE board). So I read this as meaning I shouldn't see any activity in the ICE's Quit mode (because the signals are isolated from the host system), but may see activity if I probe the Z80 on the ICE board.

SteveBagley
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Re: Fixing a Superbrain up

Postby SteveBagley » Fri May 12, 2017 9:40 am

jonb wrote:My probes are on the Z80 socket on the Superbrain board, not on the Z80 itself (mounted on the ICE board). So I read this as meaning I shouldn't see any activity in the ICE's Quit mode (because the signals are isolated from the host system), but may see activity if I probe the Z80 on the ICE board.


I wonder if the ICE keeps REFRESH alive to keep the memory contents intact?

Looking at the schematic you posted earlier -- both RFSH and MREQ are pulled up by the resistor pack Z44 so I wonder if that is faulty?

Steve

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jonb
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Re: Fixing a Superbrain up

Postby jonb » Fri May 12, 2017 9:47 am

SteveBagley wrote:
jonb wrote:My probes are on the Z80 socket on the Superbrain board, not on the Z80 itself (mounted on the ICE board). So I read this as meaning I shouldn't see any activity in the ICE's Quit mode (because the signals are isolated from the host system), but may see activity if I probe the Z80 on the ICE board.


I wonder if the ICE keeps REFRESH alive to keep the memory contents intact?

Looking at the schematic you posted earlier -- both RFSH and MREQ are pulled up by the resistor pack Z44 so I wonder if that is faulty?

Steve


Hi Steve

ICE must be doing the /RFSH signal otherwise yes, the RAM's content would be lost. But /MREQ definitely shouldn't be active when I am not accessing the RAM or ROM (as is the case here). If Z44 (resistor pack) was defective, what would you think we might see on the trace?

[Edit: Looks OK. I measure 10k between pin 16 (+5v) and 6 (/MREQ) and between 16 and 14 (/RFSH), and 20k between 6 and 14.]

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jonb
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Re: Fixing a Superbrain up

Postby jonb » Fri May 12, 2017 10:07 am

Three consecutive dumps with a zeroed EEPROM:

Err ===> d 0,400

0000 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0010 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0020 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0030 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0040 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0050 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0060 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0070 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0080 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0090 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
00A0 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
00B0 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
00C0 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
00D0 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
00E0 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
00F0 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0100 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0110 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0120 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0130 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0140 00 00 00 00 00 00 00 00-00 00 00 00 00 01 00 00 ................
0150 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0160 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0170 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0180 00 00 00 00 00 00 00 00-00 00 00 00 01 00 00 00 ................
0190 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
01A0 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
01B0 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
01C0 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
01D0 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
01E0 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
01F0 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0200 01 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0210 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0220 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0230 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0240 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0250 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0260 00 01 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0270 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0280 00 00 00 01 00 00 00 00-01 01 00 00 00 00 00 00 ................
0290 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
02A0 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
02B0 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
02C0 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
02D0 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
02E0 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
02F0 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0300 00 00 00 00 00 00 00 00-01 00 00 00 00 00 00 00 ................
0310 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0320 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0330 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0340 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0350 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0360 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0370 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0380 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0390 00 00 00 00 00 00 00 00-00 00 00 01 00 00 00 00 ................
03A0 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
03B0 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
03C0 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
03D0 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
03E0 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
03F0 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0400 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................

OK ===> d 0,400

0000 00 00 00 00 00 00 00 00-00 08 00 00 00 00 00 00 ................
0010 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0020 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0030 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0040 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 01 ................
0050 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0060 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0070 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0080 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0090 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
00A0 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
00B0 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
00C0 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
00D0 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
00E0 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
00F0 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0100 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0110 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0120 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0130 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0140 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0150 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0160 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0170 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0180 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0190 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
01A0 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
01B0 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
01C0 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
01D0 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
01E0 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
01F0 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0200 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0210 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0220 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0230 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0240 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0250 00 00 00 00 00 00 00 00-00 00 00 01 00 00 00 00 ................
0260 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0270 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0280 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0290 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
02A0 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
02B0 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
02C0 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
02D0 00 00 00 01 00 00 00 00-00 00 00 00 00 00 00 00 ................
02E0 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
02F0 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0300 00 00 00 01 00 00 00 00-00 00 00 00 00 00 00 00 ................
0310 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0320 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0330 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0340 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0350 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0360 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0370 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0380 00 00 00 01 00 00 00 00-00 00 00 00 08 00 00 00 ................
0390 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
03A0 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
03B0 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
03C0 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
03D0 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
03E0 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
03F0 00 00 00 00 00 00 00 00-00 00 00 00 01 00 00 00 ................
0400 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................

OK ===> d 0,400

0000 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0010 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0020 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0030 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0040 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0050 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0060 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0070 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0080 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0090 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
00A0 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
00B0 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
00C0 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
00D0 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
00E0 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
00F0 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0100 00 00 00 00 00 01 00 00-00 00 00 00 00 00 00 00 ................
0110 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0120 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0130 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0140 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0150 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0160 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0170 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0180 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0190 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
01A0 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
01B0 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
01C0 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
01D0 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
01E0 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
01F0 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0200 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 01 ................
0210 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0220 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0230 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0240 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0250 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0260 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0270 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0280 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0290 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
02A0 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
02B0 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
02C0 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
02D0 00 00 00 01 00 00 00 00-00 00 00 00 00 00 00 00 ................
02E0 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
02F0 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0300 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0310 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0320 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0330 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0340 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0350 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0360 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0370 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0380 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0390 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
03A0 00 00 00 00 00 00 00 00-00 00 00 01 00 00 00 00 ................
03B0 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
03C0 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
03D0 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
03E0 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
03F0 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0400 00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................

OK ===>

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jonb
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Re: Fixing a Superbrain up

Postby jonb » Fri May 12, 2017 10:16 am

With the EEPROM set to all FF, I get no errors and the memory detect is reporting the ROM properly. It looks like some spurious 1s are appearing on the databus during ROM access.

Here is a three way compare of the three dumps in my earlier post:

d01 vs d02 vs d03.JPG
Dump 1, 2, 3 three way compare

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hoglet
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Re: Fixing a Superbrain up

Postby hoglet » Fri May 12, 2017 10:49 am

Jon,

Instead of triggering of MREQ, can you trigger of CPU2BusEnable, or is that also active all the time?

Can you also set all the channels to the same vertical scale, or it will get confusing...

Dave
Last edited by hoglet on Fri May 12, 2017 10:51 am, edited 1 time in total.

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Re: Fixing a Superbrain up

Postby jonb » Fri May 12, 2017 10:50 am

I zoomed one of the earlier traces out a bit and saw this:

DS1Z_QuickPrint26.png
Y-/MREQ, C=CPU2 BUS ENA, M=/REFSH, B=D0 (CPU1)


The rising edge of D0 (in the red square) looks very wrong indeed. Moreover, this is when the Z80 is supposed to be halted.

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Re: Fixing a Superbrain up

Postby hoglet » Fri May 12, 2017 10:54 am

That slow rising edge on D0 is fine, it just means nothing is actively driving the bus at that time.

MREQ doesn't seem to be active all the time in that last scope shot. What did you do differently?

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Re: Fixing a Superbrain up

Postby jonb » Fri May 12, 2017 10:55 am

hoglet wrote:Jon,

Instead of triggering of MREQ, can you trigger of CPU2BusEnable, or is that also active all the time?

Can you also set all the channels to the same vertical scale, or it will get confusing...

Dave


it's active all the time when in quit mode :?

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Re: Fixing a Superbrain up

Postby jonb » Fri May 12, 2017 10:57 am

hoglet wrote:That slow rising edge on D0 is fine, it just means nothing is actively driving the bus at that time.

MREQ doesn't seem to be active all the time in that last scope shot. What did you do differently?


Nothing, it is just zoomed right out. I wanted to see when/if the signals were released.

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Re: Fixing a Superbrain up

Postby 1024MAK » Fri May 12, 2017 11:01 am

jonb wrote:I zoomed one of the earlier traces out a bit and saw this:

DS1Z_QuickPrint26.png

The rising edge of D0 (in the red square) looks very wrong indeed. Moreover, this is when the Z80 is supposed to be halted.

That looks like a line that was driven low, but the driver has gone tri-state (hi-z) and a pull-up is now gently pulling it to +5V, the stray capacitance causing the slow rise in the waveform.

Mark
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Re: Fixing a Superbrain up

Postby 1024MAK » Fri May 12, 2017 11:05 am

Jon, have you tried a super simple program in the EEPROM (just a JP 0000 instruction at address 0000) and a normal Z80 CPU to see if that makes any difference?

Mark
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Re: Fixing a Superbrain up

Postby jonb » Fri May 12, 2017 11:08 am

Another trace, this time a proper memory access (repeatedly doing d 0,400 in the ICE)

DS1Z_QuickPrint27.png
Y-/MREQ, C=CPU2 BUS ENA, M=/REFSH, B=D0 (CPU1)


Compare it with this which is the "idle" trace:

DS1Z_QuickPrint28.png
Y-/MREQ, C=CPU2 BUS ENA, M=/REFSH, B=D0 (CPU1)

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Re: Fixing a Superbrain up

Postby jonb » Fri May 12, 2017 11:10 am

1024MAK wrote:Jon, have you tried a super simple program in the EEPROM (just a JP 0000 instruction at address 0000) and a normal Z80 CPU to see if that makes any difference?

Mark


No, but then I can't be sure I will actually get a jp 0 when I run it, because the data bus appears to be getting corrupted.

If I put a Z80 in the CPU1 socket instead of the ICE... hmm... I can see what the probes say but not what is actually in memory. Is that what you mean?

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hoglet
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Re: Fixing a Superbrain up

Postby hoglet » Fri May 12, 2017 11:28 am

Jon,

I'm sorry, but I don't understand why the ICE is making a bunch of memory accesses when idle.

Do you?

Could you try the following:
- Channel 1 = /MREQ
- Channel 2 = /CPU2BusEnable
- Channel 3 = D0 on the ROM
- Channel 4 = D0 on the Z80 (CPU#1)

- Trigger of the falling edge of channel 2

- Set the horizontal timebase to 100ns/division

- Set the persistence to infinite

- Start the scope capturing

- Do a D 0,400

- Stop capturing

What I'm trying to do is get a detailed view of what's going on inside a each ROM read cycle

Dave

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hoglet
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Re: Fixing a Superbrain up

Postby hoglet » Fri May 12, 2017 11:36 am

Just been reading the ICE Manual:
http://www.tauntek.com/ICEMan.pdf

When the ICE is in Quit mode, the Z80 executes bursts of NOP instructions to provide for refresh of any DRAM
present in the target system. This takes up about 25% of the processor’s time, so if you know that your system
doesn’t use DRAM, you may want to disable refresh to speed up instruction tracing. In Go mode, the Z80 is
executing at full speed, so no extra refresh provision is needed.

It's possible that the bursts of ICE refresh are confusing matters here.

You can disable this with the DR (disable refresh) command.

Dave

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Re: Fixing a Superbrain up

Postby jonb » Fri May 12, 2017 11:58 am

I put D0 (ROM) on the cyan line. Looks completely wrong.

DS1Z_QuickPrint29.png
Y-/MREQ, C=CPU2 BUS ENA, M=D0 (ROM), B=D0 (CPU1)


This is in Quit mode.

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Re: Fixing a Superbrain up

Postby jonb » Fri May 12, 2017 12:07 pm

hoglet wrote:Just been reading the ICE Manual:
http://www.tauntek.com/ICEMan.pdf

When the ICE is in Quit mode, the Z80 executes bursts of NOP instructions to provide for refresh of any DRAM
present in the target system. This takes up about 25% of the processor’s time, so if you know that your system
doesn’t use DRAM, you may want to disable refresh to speed up instruction tracing. In Go mode, the Z80 is
executing at full speed, so no extra refresh provision is needed.

It's possible that the bursts of ICE refresh are confusing matters here.

You can disable this with the DR (disable refresh) command.

Dave


With refresh disabled, I get nothing. Accessing the memory with a trigger on the falling edge of /MREQ gives this:

DS1Z_QuickPrint30.png
Y-/MREQ, C=CPU2 BUS ENA, M=D0 (ROM), B=D0 (CPU1)


Again that odd shape of the D0 pulse at the ROM. And a glitch in all signals about 1/3 of the way through /MREQ.

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Re: Fixing a Superbrain up

Postby jonb » Fri May 12, 2017 12:44 pm

hoglet wrote:Could you try the following:
- Channel 1 = /MREQ
- Channel 2 = /CPU2BusEnable
- Channel 3 = D0 on the ROM
- Channel 4 = D0 on the Z80 (CPU#1)

- Trigger of the falling edge of channel 2

- Set the horizontal timebase to 100ns/division

..done. 100ns looks a bit too high resolution?

hoglet wrote:- Set the persistence to infinite
- Start the scope capturing


I don't know how to do this :(

The Rigol's got an acquire menu but I don't know what it does. It's got a lousy manual!

When I want to do something like this I usually set the time base to something huge like 1/2s then use the zoom to look at signals of interest.

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Re: Fixing a Superbrain up

Postby 1024MAK » Fri May 12, 2017 12:50 pm

jonb wrote:
1024MAK wrote:Jon, have you tried a super simple program in the EEPROM (just a JP 0000 instruction at address 0000) and a normal Z80 CPU to see if that makes any difference?

Mark


No, but then I can't be sure I will actually get a jp 0 when I run it, because the data bus appears to be getting corrupted.

If I put a Z80 in the CPU1 socket instead of the ICE... hmm... I can see what the probes say but not what is actually in memory. Is that what you mean?

It takes the ICE completely out of the system so if you still get strange things occuring, it's a circuitry fault.
With such a simple program, you can use your 'scope to monitor /MREQ and A2. Note that A2 will go high during refresh.

Code: Select all

addess 0000 C3 (op code for JP)
0001 00 (address to jump to)
0002 00 (address to jump to)
0003 00 (NOP) (should never get here!)
0004 00 address line A2 should never go high when /MREQ low.


If the data bus is corrupted by a zero bit going high, there is a very good chance that the CPU will fall out of the loop...
Of course, it could jump past 0004, so fill the rest of the ROM with zeros, and at some point A2 will go high.

Mark
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Re: Fixing a Superbrain up

Postby hoglet » Fri May 12, 2017 1:01 pm

jonb wrote:I don't know how to do this :(

The Rigol's got an acquire menu but I don't know what it does. It's got a lousy manual!

I posted links to the relevant sections of the manual earlier.

Does the manual I linked match your scope?

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Re: Fixing a Superbrain up

Postby 1024MAK » Fri May 12, 2017 1:13 pm

jonb wrote:With refresh disabled, I get nothing. Accessing the memory with a trigger on the falling edge of /MREQ gives this:

DS1Z_QuickPrint30.png

Again that odd shape of the D0 pulse at the ROM. And a glitch in all signals about 1/3 of the way through /MREQ.

The magenta (D0 ROM) trace is strange. Are you using DC or AC coupling? Only after the first positive going pulse, it never goes back to a proper logic low level.

Mark
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Re: Fixing a Superbrain up

Postby jonb » Fri May 12, 2017 1:14 pm

1024MAK wrote:
jonb wrote:With refresh disabled, I get nothing. Accessing the memory with a trigger on the falling edge of /MREQ gives this:

DS1Z_QuickPrint30.png

Again that odd shape of the D0 pulse at the ROM. And a glitch in all signals about 1/3 of the way through /MREQ.

The magenta (D0 ROM) trace is strange. Are you using DC or AC coupling? Only after the first positive going pulse, it never goes back to a proper logic low level.

Mark


DC coupling.
Last edited by 1024MAK on Fri May 12, 2017 1:21 pm, edited 1 time in total.
Reason: Edited to correct the quote of my post, in which I messed up the quote from Jon, do'h!

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Re: Fixing a Superbrain up

Postby 1024MAK » Fri May 12, 2017 1:25 pm

Strange indeed. Digital (TTL like) signals should be either logic low (0V to 0.8V), logic high (2V to 5V), or in the case of a signal line connected to tri-state buffers, float upwards towards 5V (most typical, but floating downwards to 0V is also possible).

You should not have control signals with more than two levels :shock:

Mark
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Re: Fixing a Superbrain up

Postby hoglet » Fri May 12, 2017 1:26 pm

Just a random thought....

The errors were (almost) all on the lower 4 bits of the data bus.

There is a 2114 (Z88) sharing the CPU2 data bus with the ROM that sits on bits 3..0.

In my experience, 2114's frequently fail. Probably the number one cause of a dead atom.

But check the chip select first before ripping it out.

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Re: Fixing a Superbrain up

Postby jonb » Fri May 12, 2017 1:30 pm

Sorry Dave, I missed your post about setting the 'scope up. Thanks for your advice again - I've done it now, and here is what I think is the pertinent trace.

DS1Z_QuickPrint31.png
Y-/MREQ, C=CPU2 BUS ENA, M=D0 (ROM), B=D0 (CPU1)


The CPU is reading repeatedly from the ROM with FF in all locations, using the following command line

> D 0,400;z 9;rl

..which is essentially a loop of continuous reads with a short delay.

Without the refresh signal we get a single cycle of:

DS1Z_QuickPrint32.png
Y-/MREQ, C=CPU2 BUS ENA, M=D0 (ROM), B=D0 (CPU1)


..and this looks the same as the other traces I posted. It's a lot cleaner (there are no overlaid signals, they seem to be artefacts of the ICE refresh) and it still has the dodgy cyan line and little spike 1/3 of the way through /MREQ.

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Re: Fixing a Superbrain up

Postby jonb » Fri May 12, 2017 1:32 pm

hoglet wrote:Just a random thought....

The errors were (almost) all on the lower 4 bits of the data bus.

There is a 2114 (Z88) sharing the CPU2 data bus with the ROM that sits on bits 3..0.

In my experience, 2114's frequently fail. Probably the number one cause of a dead atom.

But check the chip select first before ripping it out.


What, that it is getting CS-ed?

I have some of those chips (from an atom that has RAM/ROM fitted) and could swap them out. I ran a logic probe on the shared /CS line (the /CS coming from Z70 pin 11) and it is pulsing when I access the ROM. This signal is generated by Z77 and Z70. I replaced Z77 already, but maybe the inverter of Z70 is stuck. It is supposed to output /A15 , but when I probe the gate both sides are LOW. Stuck, perhaps?

Continuity check indicates that pins 11 and 10 of the LS04 (Z70) are both grounded. I think the chip has popped.
Last edited by jonb on Fri May 12, 2017 1:50 pm, edited 1 time in total.

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Re: Fixing a Superbrain up

Postby hoglet » Fri May 12, 2017 1:46 pm

jonb wrote:The CPU is reading repeatedly from the ROM with FF in all locations, using the following command line

> D 0,400;z 9;rl

..which is essentially a loop of continuous reads with a short delay.

Without the refresh signal we get a single cycle of:

Arrgh, it's so hard doing this kind of debugging remotely!

I guess I'm still not really understanding what this ICE is doing. If the ICE is in a loop continually reading, why aren't we seeing multiple reads on the scope.

(It may be the ICE is reading very slowly, as printing to a serial port could be the limiting factor)

If you zoom the time base out, is there any evidence of multiple reads?

I'm trying to get to a point where in the ICE you dump N locations, and on the scope you see some evidence of N ROM read cycles.

Then we can try to zoom in to look at each read cycle.

Also, why test with the ROM full of FF's? This case read back correctly.

Dave
Last edited by hoglet on Fri May 12, 2017 1:50 pm, edited 1 time in total.

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Re: Fixing a Superbrain up

Postby hoglet » Fri May 12, 2017 1:48 pm

jonb wrote:What, that it is getting CS-ed?

I meant check it wasn't being selected (unless you expect it should be?)

Dave


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