Fixing a Superbrain up

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jonb
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Fixing a Superbrain up

Postby jonb » Mon Apr 10, 2017 5:40 pm

Hi

After sorting the Superbrain's power supply, I am now looking at the logic board. This thing has two Z-80 CPUs - one handles the disk drives (including loading the boot sector), the other is the general purpose CPU.

Here is a detailed schematic. https://drive.google.com/open?id=0B-xze ... 3R1bVBiT0E

So, I have connected my Z80-ICE to CPU 1 and had a poke around. I can see big memory problems, so I checked CAS and RAS lines (4 of each, for the foutrbanks of 16k) and discovered that CAS 1 and CAS 2 are stuck high. Traced that back to the 74LS155 to the left of the RAM banks (coloured cyan in the schematic). It has pulsing inputs, but no outputs on pins 5 & 6 (CAS_1, CAS_2 respectively). New 155 on order!

Manwhile, I've done some testing with the ICE which seems to indicate that every bank is having problems.

The tests comprise setting the first page of each 16K block to FF then 00 and looking at the results.

Boot and look at the first page of memory:

Code: Select all

Z80 ICE V0.72 Jun 21, 2011 R. Grieb/Tauntek

OK ===> d 0

0000   30 00 88 F0 50 C2 10 00-30 01 88 00 A0 C0 10 00    0...P...0.......
0010   C0 20 00 20 00 00 11 00-C0 00 00 00 E0 B0 C0 00    . . ............
0020   C0 30 00 80 30 00 30 00-80 32 00 88 30 00 88 20    .0..0.0..2..0..
0030   00 80 D0 10 30 00 00 D0-08 30 00 32 00 80 30 00    ....0....0.2..0.
0040   80 30 00 80 B0 C0 41 00-30 20 D0 00 A0 30 00 80    .0....A.0 ...0..
0050   32 00 8A 30 00 80 E0 03-00 04 30 00 00 C0 60 00    2..0......0...`.
0060   00 C0 50 00 E0 00 30 00-88 30 05 80 00 D0 23 00    ..P...0..0....#.
0070   70 00 20 32 05 80 30 00-80 60 20 30 03 88 30 01    p. 2..0..` 0..0.



Now set it to FF:

Code: Select all

OK ===> f 0,7f ff

OK ===> d 0

0000   FF FF FF FF FF FF FF FF-FF FF FF FF FF FF FF FF    ................
0010   FF FF FF FF FF FF FF FF-FF FF FF FF FF FF FF FF    ................
0020   FF FF FF FF FF FF FF FF-FF FF FF FF FF FF FF FF    ................
0030   FF FF FF FF FF FF FF FF-FF FF FF FF FF FF FF FF    ................
0040   FF FF FF FF FF FF FF FF-FF FF FF FF FF FF FF FF    ................
0050   FF FF FF FF FF FF FF FF-FF FF FF FF FF FF FF FF    ................
0060   FF FF FF FF FF FF FF FF-FF FF FF FF FF FF FF FF    ................
0070   FF FF FF FF FF FF FF FF-FF FF FF FF FF FF FF FF    ................



So far, so good. Back to zero then:

Code: Select all

OK ===> f 0,7f 0

OK ===> d 0

0000   30 00 88 20 50 C0 13 00-30 00 88 F0 A0 C2 10 00    0.. P...0.......
0010   C0 20 00 20 00 04 10 00-C0 00 00 04 E0 B0 C0 00    . . ............
0020   C0 30 00 80 30 00 30 00-80 30 01 80 30 00 80 00    .0..0.0..0..0...
0030   00 80 D0 10 30 20 00 C0-00 30 00 30 0C 8A 31 00    ....0 ...0.0..1.
0040   80 30 00 80 B0 C0 41 00-30 20 D0 08 00 30 00 80    .0....A.0 ...0..
0050   30 00 80 20 00 80 E0 01-40 00 30 00 00 C0 60 00    0.. ....@.0...`.
0060   00 C0 50 00 E0 00 32 00-88 30 00 80 00 D0 23 00    ..P...2..0....#.
0070   70 00 00 30 00 80 30 00-80 40 20 30 03 80 30 00    p..0..0..@ 0..0.


Oh dear..

Bank 1: 4000h

Code: Select all


OK ===> f 4000,407f ff

OK ===> d 4000

4000   FF FF FF FF FF FF FF FF-FF FF FF FF FF FF FF FF    ................
4010   FF FF FF FF FF FF FF FF-FF FF FF FF FF FF FF FF    ................
4020   FF FF FF FF FF FF FF FF-FF FF FF FF FF FF FF FF    ................
4030   FF FF FF FF FF FF FF FF-FF FF FF FF FF FF FF FF    ................
4040   FF FF FF FF FF FF FF FF-FF FF FF FF FF FF FF FF    ................
4050   FF FF FF FF FF FF FF FF-FF FF FF FF FF FF FF FF    ................
4060   FF FF FF FF FF FF FF FF-FF FF FF FF FF FF FF FF    ................
4070   FF FF FF FF FF FF FF FF-FF FF FF FF FF FF FF FE    ................

OK ===> f 4000,4077 0

OK ===> d 4000

4000   00 80 90 80 90 80 90 A0-90 80 90 80 90 A0 80 00    ................
4010   90 80 91 80 80 00 91 80-91 80 91 00 80 A0 80 20    ...............
4020   04 98 04 98 04 90 1C 90-04 90 0C 90 0C 90 1C 90    ................
4030   14 90 0C 90 0C 90 00 90-9C 90 0C 90 1C 90 10 90    ................
4040   0C 98 0C 98 04 98 0C 98-04 98 0C 90 0C 90 18 90    ................
4050   04 98 0C 90 1C 90 0C 10-1C 90 0C 90 1C 90 0C 90    ................
4060   DF 98 DF 90 DF 90 DF 90-DF 98 DF 90 D9 90 DF 90    ................
4070   DF 98 DF 98 DF 90 DF 90-FF FF FF FF FF FF FF FE    ................



Also bad. On to the next bank...

Code: Select all


OK ===> f 8000,807f ff

OK ===> d 8000

8000   FF FF FF FF FF FF FF FF-FF FF FF FF FF FF FF FF    ................
8010   FF FF FF FF FF FF FF FF-FF FF FF FF FF FF FF FF    ................
8020   FF FF FF FF FF FF FF FF-FF FF FF FF FF FF FF FF    ................
8030   FF FF FF FF FF FF FF FF-FF FF FF FF FF FF FF FF    ................
8040   FF FF FF FF FF FF FF FF-FF FF FF FF FF FF FF FF    ................
8050   FF FF FF FF FF FF FF FF-FF FF FF FF FF FF FF FF    ................
8060   FF FF FF FF FF FF FF FF-FF FF FF FF FF FF FF FF    ................
8070   FF FF FF FF FF FF FF FF-FF FF FF FF FF FF FF FF    ................

OK ===> f 8000,807f 0

OK ===> d 8000

8000   00 D4 DC C4 D8 C4 DC C4-DE C4 DC C4 04 84 5C C4    ..............\.
8010   DE D4 D8 C4 DC 84 DC 00-DC D4 DC C4 84 C4 1C C4    ................
8020   00 D0 01 D0 40 D0 40 D8-41 D1 10 D0 40 D0 10 D0    ....@.@.A...@...
8030   42 D8 40 D1 00 D0 51 D0-51 50 10 D4 41 D0 40 50    B.@...Q.QP..A.@P
8040   00 D9 01 DC 01 DC 50 D8-01 D9 43 D0 00 D8 40 D0    ......P...C...@.
8050   41 D4 50 DC 51 DC 00 D4-51 DC 53 D4 52 D4 50 D4    A.P.Q...Q.S.R.P.
8060   52 D9 51 D0 53 D0 01 D0-51 D0 53 D4 51 D0 50 D0    R.Q.S...Q.S.Q.P.
8070   51 D0 51 D0 59 D4 59 D4-51 D0 51 D0 59 D4 59 D0    Q.Q.Y.Y.Q.Q.Y.Y.



Final bank.

Code: Select all

OK ===> f c000,c007f ff

OK ===> d c000

C000   FF 65 FF 65 FF 65 FF 65-FF 65 FF 65 FF 65 FF 65    .e.e.e.e.e.e.e.e
C010   FF 65 FF 65 FF 65 FF 65-FF 65 FF 65 FF 65 FF 64    .e.e.e.e.e.e.e.d
C020   FF 35 FF 3D FF 35 FF 71-FF 35 FF 7D FF 75 FF 75    .5.=.5.q.5...u.u
C030   FF 35 FF 35 FF 75 FF 75-FF 35 FF 75 FF 75 FF 75    .5.5.u.u.5.u.u.u
C040   FF 3D FF 3D FF 3D FF 7D-FF 3D FF 7D FF 7D FF 7D    .=.=.=...=......
C050   FF 3D FF 7D FF 7D FF 7D-FF 3D FF 7D FF 7D FF 7D    .=.......=......
C060   FF 3D FF 75 FF 75 FF 75-FF 35 FF 75 FF 75 FF 75    .=.u.u.u.5.u.u.u
C070   FF 35 FF 75 FF 75 FF 75-FF 35 FF 75 FF 75 FF 34    .5.u.u.u.5.u.u.4

OK ===> f c000,c00ff 0

OK ===> d c000

C000   FF 65 FF 65 FF 65 FF 65-FF 65 FF 65 FF 65 FF 65    .e.e.e.e.e.e.e.e
C010   FF 65 FF 65 FF 65 FF 65-FF 65 FF 65 FF 65 FF 64    .e.e.e.e.e.e.e.d
C020   FF 35 FF 3D FF 3D FF 71-FF 35 FF 7D FF 7D FF 75    .5.=.=.q.5.....u
C030   FF 35 FF 3D FF 75 FF 75-FF 35 FF 75 FF 75 FF 75    .5.=.u.u.5.u.u.u
C040   FF 3D FF 3D FF 3D FF 7D-FF 3D FF 7D FF 7D FF 7D    .=.=.=...=......
C050   FF 3D FF 7D FF 7D FF 7D-FF 3D FF 7D FF 7D FF 7D    .=.......=......
C060   FF 3D FF 75 FF 75 FF 75-FF 35 FF 75 FF 75 FF 75    .=.u.u.u.5.u.u.u
C070   FF 35 FF 75 FF 75 FF 75-FF 35 FF 75 FF 75 FF 34    .5.u.u.u.5.u.u.4



Looks even worse - no response at all.

I think at least 2 banks should work properly, given they are getting CAS/RAS signals, so I have to consider that some of the RAM is bad. Quite a bit of it, I expect, but there is no pattern emerging yet. It just looks like every single RAM chip is bad. I suppose the thing to do wpould be to concentrate on one bank and see if I can get that running. I have a reasonable stock of 4116s here.

But I can't help thinking that something else is wrong. There are too many failed chips.

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Re: Fixing a Superbrain up

Postby 1024MAK » Mon Apr 10, 2017 6:15 pm

Are the three supplies (+5V, +12V and -5V) present on all the 4116 DRAM chips?
Only loss of the -5V rail while the positive supplies are present is a known cause of chip failure :(

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Re: Fixing a Superbrain up

Postby jonb » Tue Apr 11, 2017 5:50 am

They are present now, Mark, but who knows what happened when the power supply blew?

Although to be fair, that was on the HV side.

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Re: Fixing a Superbrain up

Postby jonb » Wed Apr 12, 2017 5:41 pm

So.. investigation proceeds along the lines of "order new LS155 to fix CAS2/3" and look at the other processor in the meantime.

CPU2 is next to the boot ROM, and handles disk I/O. And it is stuck in RESET so not much is going on there.

A lot of faffing around with the ICE (it won't run in CPU2's socket) and poking about with the logic probe. /RESET is stuck low. It's fed by the PC3 output of the 8255 via an inverter but something has to program the thing to get it to drop the (default on reset) logic high on its output.

In amongst all this stuff id the ROM chip, which tends to fail and lose its content over time. But this one is a TMS2716C which my programmer doesn't recognise (indeed, most don't as it needs +5v, -5v and -12v to function). However it is nearly pin compatible with a 2816 EEPROM and so with an adapter you can use the more modern chip and stick some ROM goodness on there, which I have done, using a downloaded Superbrain QD ROM v3.1.

I am now seeing the CPU2 /RESET line release after power on, hooray! But the ICE still doesn't like it, boo!

Despite this minor achievement nothing much else is happening. Maybe because the main RAM is all toasted, or maybe because the power supply is a bit "dirty". I'm getting ~850mV noise around the 5v line on my scope, probably becasue the capacitors in the power board haven't been replaced. And this is, I fear, why the RAM has failed. There is a post on VCF where a member says the RAM doesn't work reliably on his 'brain unless the 5v rail is at 5.2v. Interesting. So if I get a 400mv swing + or - around the 5v point, I will see the 4116s start to fail. So on Bryce's advice I ordered a full set of replacement caps for the power board so that the power can be smoothed properly.

I have fixed the broken Y key now...!

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Re: Fixing a Superbrain up

Postby 1024MAK » Wed Apr 12, 2017 8:27 pm

As far as I can tell, the main supply for 4116 DRAM chips is the +12V. The +5V appears to only supply the input / output interface circuitry.

Mark
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Re: Fixing a Superbrain up

Postby jonb » Thu Apr 13, 2017 7:30 am

Hi Mark

I haven't looked at the +12v supply yet, but I suspect it is just as noisy... hang on..

DS1Z_QuickPrint3.png
SB 12v rail


Yeah, pretty nasty! Here's the 5v rail for comparison, it is much worse, especially if we view the spikes in terms of a percentage of the target voltage.

DS1Z_QuickPrint4.png
SB 5v rail


My point is, the componentry - not just the DRAM - must be getting stressed by these dirty supplies, and I've encountered some inconsistent behaviour (notably in CPU2's reset sequence), so it seems proper to sort the power out first. It's a possible explanation as to why I had something on the screen when I first got the power supply running; this meant the display chip was being initialised properly even if the machine hadn't booted all the way.

The implications of that are that a) the machine started correctly, b) the ROM is (probably) intact, c) all the video generation circuitry is OK, d) at least one CPU is OK. When I first saw it, I thought it was bad RAM.

SB coming back to life.jpg
Screen up...


But then, as I said before, the next time I powered it up, it was all blank, and I wonder if this failure is a result of the power supply.

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Re: Fixing a Superbrain up

Postby 1024MAK » Thu Apr 13, 2017 9:57 am

Spikes that are within the maximum acceptable voltage range don't stress the circuitry. However, they will cause havoc with the logic, especially with anything that switches on an edge, or which uses flip-flops (counters, latches, memory, CPUs etc...).

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Re: Fixing a Superbrain up

Postby 1024MAK » Thu Apr 13, 2017 10:01 am

Keep in mind also, that electrolytic capacitors and some semiconductor devices may work okay when first switched on, but the switch-on stress on components that were already degraded may well finish them off. So the next time you power up, it's even less functional :(

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Re: Fixing a Superbrain up

Postby jonb » Thu Apr 13, 2017 10:53 am

All good points, Mark.

Looking at those scope traces, would you agree that these power supplies are too dirty to rely on?

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Re: Fixing a Superbrain up

Postby 1024MAK » Thu Apr 13, 2017 3:53 pm

For digital logic systems. With a good supply, when measured at the PSU output termanals, I would expect 100mV or less.
Note CPU systems generate a lot of electrical noise.
So yes there is a lot of noise on both those supply rails. Where exactly are you measuring?

You should use a good 0V (GND) connection, preferably the PSU 0V connection or the main power wiring connection to the main board.

Things to investigate (in this order):
  • Renew the secondary side (output) electrolytic capacitors,
  • Check / test any and all connectors between the PSU and the circuitry for poor connections,
  • Renew any "bulk" decoupling electrolytic capacitors on the main logic board,
  • Visually inspect the power traces on the PCB and visually check disc ceramic decoupling capacitors for damage,
  • If none of that helps, stop the digital circuitry (disable the clock generator) to see what effect this has on the noise.
  • use your 'scope to see if you can determine which circuitry is causing the worst of the noise.

Mark
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Re: Fixing a Superbrain up

Postby jonb » Sat Apr 15, 2017 3:11 pm

Okay dokey.

Having repaired the power supply (see viewtopic.php?f=45&t=12871), we now turn our attention to the main board, and CPU1's poorly DRAM. CAS now missing on three banks, so it's time to trace back with a logic probe and see what's failed. This is the fun part.

CAS 1,2 and 3 are missing. They are generated by Z35, a 74LS155 and I can see pulses going in, but nothing coming out. A replacement is definitely in order!

IMG_0858.JPG
Sorted...


The Superbrain's main board has good sized drill holes in its pads, which makes desoldering the chips quite easy - the suction can get all round the pin easily.

Power up and we are back in the game!

IMG_0859.JPG
We have lift off! Sort of.


Time for the ICE (,ICE, baby...).

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Re: Fixing a Superbrain up

Postby jonb » Sat Apr 15, 2017 3:37 pm

OK, it is still intermittent.

CPU2 is getting stuck in reset. Not entirely sure why. When it comes out of reset, we get a picture, and we can look at CPU1's memory. Using the ICE's MD )memory detect) command repeatedly, we get different results every time. And one of the CAS lines has got stuck again.

Hmmm... I'm concerned that the LS155 has popped a channel again, and wondering what might have caused it.

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Re: Fixing a Superbrain up

Postby jonb » Sun Apr 16, 2017 10:22 am

After some investigation with the scope, I can see all CAS lines giving signals. Perhaps it i something to do with the ICE.

I can also see that the ROM is being accessed by CPU1 at startup, but it's first instruction is not working properly. There must be something going on with the DRAM. I will take it all out and build bank 0 up.

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Re: Fixing a Superbrain up

Postby jonb » Sun Apr 16, 2017 8:23 pm

Now the CAS has gone again. Intermittent.

Today I have ripped all the RAM out, soldered in new sockets and put new RAM into the machine.

IMG_0862.JPG


What a palaver. Only lost three pads and one track, I was quite pleased with myself.

I am now getting a full screen of garbage reliably (every reset), so the VDP is definitely getting initialised. CAS 1 & 2 are still bad. Have replaced the LS157 and LS155 that generate them, but no joy. My ICE thinks that it is all R/O memory, where it thinks there is memory at all, but each time I test it I get a different result. I mean, all R/O but the gaps ("no memory detected") move each time.

On fitting all the RAM sockets, I tested the voltages. I see 4.75v, 12.75v, -5.23v on the power lines. Thinking of upping the 5v rail a little. Not sure. I tried to trace the signals to the CAS generation back but quickly got lost in the schematic :(

Then, as I was fiddling around, CAS2 came up and the ICE detected Bank 2 properly and it tested good. But when I reset the machine, it was gone again.

I'm out of ideas for the time being...

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Re: Fixing a Superbrain up

Postby jonb » Tue Apr 18, 2017 3:19 pm

I realised that CAS and RAS shouldn't be pulsing if the bank is not being addressed. I'd got them confused with refresh.. #-o

Most likely, I replaced all the RAM plus the LS155 for nothing, as none of it has improved matters.

I'm looking at the schematic, trying to work out what is going on. And failing... :(

Edit: I am of the suspicion that the memory won't work until some sort of switch has been flipped (via n OUT instruction). It appears that from startup, the ROM is visible starting from 0000h, but the first thing it does is to copy most of itself to C000 - then it jumps to C006 which is the boot entry point.

The problem is that if C000-FFFF (bank 03) isn't taking data, then it crashes on the jump. :evil:

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Re: Fixing a Superbrain up

Postby 1024MAK » Tue Apr 18, 2017 4:34 pm

Hi Jon

Which Z80 ICE are you using?

In most designs using 4116 DRAM chips, the DRAM /RAS goes active during /REFRESH. Can you confirm this with a 'scope?

Is the ROM socketed? If it is, is it a type where you can temporarily fit a EPROM with a simple test program? All the test program should do is to run in a tight loop reading from each address, throughout the 64k address range. You can then use your 'scope to check most of the signals.

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Re: Fixing a Superbrain up

Postby hoglet » Tue Apr 18, 2017 5:58 pm

Jon,

A few random thoughts on how to proceed....

My inclination would be to start with the ROM, as there is less that can go wrong there!

Can you see the ROM from within the ICE?

If so, then compare it with a known good dump of what the ROM should be.

If not, then try to understand why not. How is the ROM switched in and out of the memory map?

Is there a disassembly of the ROM anywhere? If not, can you post a dump from your system?

Does the ICE allow you to do IO reads/writes? If so, is there anything useful (and simple) you could look at? For example, a UART?

The idea is to slowly build up a picture of what's working and what's not working. This sort of ground data is invaluable in trying to understand where the fault lies.

It is possible the ICE is incompatible with the Superbrain. Sometimes the timings in the original system can be very tight. So another parallel tack you could take is to try to compare the system activity following reset between the the original Z80 and the ICE. The goal here would be to try to demonstrate they are both behaving (or mis-behaving) in the same way. Doing so will boost your confidence that the ICE is working correctly in this system.

Do you have one of the cheap 8-bit or 16-bit USB logic analyzsers? If so, hook it up to a few of the Z80 control signals:
- Clock (6)
- MReq (19)
- IOReg (20)
- Rd (21)
- Wr (22)
- Wait (24)
- Reset (26)
- M1 (27)

Set it on the fastest sampling rate (24MHz) and capture as long a trace as possible. Start recording just before you release reset.

Do this three times for the ICE, and three times for the Z80, and upload the results somewhere.

Dave

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Re: Fixing a Superbrain up

Postby jonb » Tue Apr 18, 2017 6:22 pm

ROM Disassembly attached.

Superbrain v3.1 ACT HDD ROM.txt
(31.58 KiB) Downloaded 23 times


Plus some of the port designations.

SB IO ports.txt
(2.26 KiB) Downloaded 19 times


I also went back to the power supply, because I know that the SB is sensitive to dirty power, and these intermittent results may be caused by noise.

I've replaced the last electrolytic capacitor in the low voltage side of the PSU - 2200 uF 16v, but all I had was a 10v part. I just put it in there temporarily; the voltage across it is 12v. Anyway, some new traces:

DS1Z_QuickPrint14.png
5v rail with dummy load


DS1Z_QuickPrint15.png
12v rail with dummy load


You can see that the 12v rail has ~30mv and the 5v rail has ~50mv swing about the target voltage. Does this look smooth enough to you? I read about two other Superbrains undergoing restoration; one of them isn't working like mine, but its owner hasn't got an ICE. He comments that he has "lots of noise on GND" (dunno how you measure that given that GND is normally your reference) and that it causes corruption. The other one does work but its owner found he had to raise the voltage to 5.2v (not sure where measured) before the RAM would work properly. He has an ICE like mine, same model. So I have adjusted my PSU so that I get a true 5v at the RAM chips (on the other side of the huge board to where the power comes in), this means it reads 5.2 at the PSU rail.

This is why I'm still thinking that the PSU is having something to do with this.

About logic analysers... you know I have the Zicon; I could use that, perhaps.

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Re: Fixing a Superbrain up

Postby 1024MAK » Wed Apr 19, 2017 8:52 am

I don't think the PSU is now the cause of the trouble. I would say that the AC component (actually AC ripple) is now within acceptable levels.

The adjustment of the +5V rail so that you get exactly +5.0V at the end of the 5V distribution tracks is sensible.

I agree with Dave in that the area to look at next is the primary CPU reading from ROM.

When I was looking at the schematic yesterday, I only saw one ROM and it is attached to the secondary CPU data bus, with a tristate buffer linking the two data buses. This ROM is an old type and requires multiple voltage rails. Have you checked that it is functioning correctly and that the data is good?

Mark
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Re: Fixing a Superbrain up

Postby jonb » Wed Apr 19, 2017 10:28 am

Yes, the TMS27C16 ROM is a bit of a git.

The socket is showing +5v at pin 24, -5v at pin 21 and 13.1v at pin 19 (a little bit high, but OK I hope - there is no way of altering it independently).

However, I am now running a 2816 EEPROM with suitably hacked-up adaptor in this socket. It's using the 5v line only.

Some more investigation reveals that CPU1 can grab CPU2's bus using /BUSREQ via the 8255. PC5 is wired to CPU2 /BUSREQ and PB7 is /BUSREQ. Seems like PC2 maps the ROM into low memory, via that clump of gates at bottom left...

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Re: Fixing a Superbrain up

Postby jonb » Wed Apr 19, 2017 3:13 pm

I still fear some paging issue. I tried swapping out the 8522 PPI chip for a known working one (out of my MZ-80A, sacrilege!) but that too has made no difference. So I am back to looking at the support logic that manages the paging. Z38, Z39, Z42, Z49, Z53, Z48 and the bus transceivers Z61, Z62, Z64. Maybe Z70 / Z77 too. As well as Z80 (I/O address decoder).

Problem with this approach is I may as well replace every chip on the board and have done with it. But then, I would never know what the problem was (always assuming that it started working!)

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Re: Fixing a Superbrain up

Postby hoglet » Wed Apr 19, 2017 3:22 pm

Jon,

I come back to one of my earlier questions. Immediately after reset, using the ICE, is the ROM visible in the memory map?

Dave

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Re: Fixing a Superbrain up

Postby jonb » Wed Apr 19, 2017 5:20 pm

Yes, at 0000h. But reading it gives unpredictable results. I can see some of the code, and occasionally it is the right code. I noted that when listing it using the ICE it sometimes looks correct, but the first time I try to step through it it goes wrong, I think because there's some garbling going on on the bus.

Once, when testing, I got a stable Bank 3 (C000-FFFF) and it tested OK. Then on next boot it was gone.

That's one of the reasons I suspected the ROM mapping logic. But it is a bit too complicated for me. If you refer to the schematic, there is a block of gates at the bottom left that appears to handle mapping, in conjunction with some of the 8522's pins (PC0, PC2 and PC4). I think PC0 disables the RAS (see the line marked RAS DISABLE, bottom left), PC2 pages ROM in and out of Bank 1 (0000-0800) and PC4 I'm not entirely sure about. These also alter the bus transceiver settings so that CPU1 can get at the ROM which is sitting on CPU2's bus.

At boot, the first thing that happens is that CPU1 copies 1/2 of the ROM (400h-800h) to RAM (C000 - C400), then jumps to the entry point (at C600h). Following this, it must switch the ROM out of CPU1's address space by sending signals to the 8522.

As I write this I have got some more info.

PPIC PORT C.JPG


So, if I wish to set it so that CPU1 has all 64K DRAM to play with, I need to OUT(6A),B8. I have tried this with the ICE and it has no effect, it is like the 8255 pins are stuck. However, when outputting FF then 00 in a loop to the same port, I see no activity on the data bus apart from one line. I have tested the address decoding for the 8522, and it appears that it is being selected properly. But it looks as if the data is not reaching it.

I suspect the bus transceivers...

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Re: Fixing a Superbrain up

Postby hoglet » Wed Apr 19, 2017 5:49 pm

jonb wrote:So, if I wish to set it so that CPU1 has all 64K DRAM to play with, I need to OUT(6A),B8. I have tried this with the ICE and it has no effect, it is like the 8255 pins are stuck. However, when outputting FF then 00 in a loop to the same port, I see no activity on the data bus apart from one line. I have tested the address decoding for the 8522, and it appears that it is being selected properly. But it looks as if the data is not reaching it.

I suspect the bus transceivers...

What's happening to pin 19 of the bus transceivers when you do the above test?

It might be worth desoldering the data bus transciever and socketing the replacement, so that with the transceiver removed you can be sure the CPU1 side of the data bus is not being interfered with by the CPU2 side.

I think a good goal would be to be able to successfully write to port C of the 8255 from the ICE.

If I get some time over the next couple of days I might try to understand the logic that's driving pin 19.

Dave

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Re: Fixing a Superbrain up

Postby jonb » Wed Apr 19, 2017 6:38 pm

My thoughts exactly, Dave.

So I took CPU's data bus transceiver out. No difference. I took every socketed chip out including the 8255, but left the ICE in CPU1's socket.

I'd done OUT (6A),0; OUT (6A),FF in a loop and tested all the data lines. Only one was pulsing. Very odd!

I then hard wired the 8255 PC output for CPU1 standard memory access and redid the test. All data lines pulsing, but the memory is still not accessible.

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Re: Fixing a Superbrain up

Postby jonb » Thu Apr 20, 2017 7:55 am

Some more traces - this time, a data line (D7) and +5v.

DS1Z_QuickPrint17.png
Yellow: D7, Cyan: +5v


The CPU is doing nothing at this point; I have just initialised the ICE. I'm guessing those pulses are refreshes, but not sure. It all looks very noisy.

DS1Z_QuickPrint18.png
Yellow: D7, Cyan: +5v


Zoomed in. Looks way too noisy?

I tried putting a fat capacitor across the 5v rail and added a ground strap. Trace now looks like this:

DS1Z_QuickPrint19.png
Yellow: D7, Cyan: +5v


Not much better. I wonder whether the logic probe is not picking up these pulses. According to the scale on the scope, the high point of the pulses is only ~2v. Shouldn't they be closer to 5v?

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Re: Fixing a Superbrain up

Postby jonb » Thu Apr 20, 2017 9:42 am

Here's another one.

DS1Z_QuickPrint20.png
Yellow=+5v, Cyan=/RFSH, Magenta=/M1, Blue=/MREQ


/RFSH and /M1 look OK voltage wise. /MREQ seems a bit wobbly.

The 5v rail looks like it is reacting (badly) to the /RFSH and /M1 pulses.

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Re: Fixing a Superbrain up

Postby jonb » Thu Apr 20, 2017 3:19 pm

I've been testing the data lines. The signals seem to be present, but none of them are showing more than ~2v peaks. I suspect this is failing to trigger any of the logic gates (in the memory or elsewhere), and might be why my probe thinks that they are not pulsing. Perhaps something is dragging the bus down, but I can't tell for sure. The only thing I can think of would be to disconnect everything from the data bus apart from the memory and start from there. It's a bit drastic, though. There are three large ICs left; the keyboard encoder and two USARTs, and none of them are socketed..

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Re: Fixing a Superbrain up

Postby jonb » Thu Apr 20, 2017 4:16 pm

Right.

I pulled the keyboard encoder chip and tried again. Looks like this is the cause of the poor data line voltages. It's a pity this is such a hard to find part.. Anyway, now I get what look like proper signals on the data bus, and I can see Bank 0 and Bank 2 at reset. Banks 1 and 4 are currently invisible.

This is, of course, wrong.

At reset I should at least be able to see the ROM in Bank 0 and the RAM in bank 2 but I can't. I put the bus transceiver and ROM back in but now I get that memory corruption thing again. For example, the first instruction in the ROM is LD A,(8800). When you step it, you get a different instruction. When you list it a second time, it has changed.

I think I shall look at the 8522, see if its outputs (that control the bank switching) are working, because it looks like RAM bank 0 isn't being disabled. I expect that what I'm seeing with the ROM changing contents randomly, is contention with the RAM.

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Re: Fixing a Superbrain up

Postby jonb » Thu Apr 20, 2017 4:20 pm

Just trying an experiment - removed Bank 0 entirely and tried to access the ROM. Still getting inconsistent results, so back to the drawing board on that. Darn it. :evil:


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