P.R.E.S. AP5 - Original and Re-Design

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daveejhitchins
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Re: P.R.E.S. AP5 - Original and Re-Design

Postby daveejhitchins » Tue Apr 11, 2017 5:02 pm

All I meant was the direction of the little red arrow on pin 74 is wrong. It's showing this pin as an output, and it's really an input I think.
BR/nW is an output to the Tube connector, 1MHz BUS connector, ROM13 and the 6522. Just a Buffered R/nW.
Can you let me have the updated pin numbers and names for these signals, and for the additional jumpers?
Updated Schematic attached. - We now have Jumpers to:
J1 - Change the right hand socket to take a 256K part > So it will now incorporate the Center IC, as well - Note: What would be the center socket IC should be in the lower half of the 256K part.
J2 - Disables ROM 13 in case of clash with a second cartridge or an AP6.
J3 - Disables the locking action for the center IC socket - Note: if J1 is closed it will disable the locking action for the lower half of the 256K part that's in the right hand IC socket.
J4 - Disables the locking action for the right hand IC socket. - Note: if J1 is closed this ROM image should be in the upper hale of the 256K part.

There is one other pinout change we should make. Could you move Phi0 onto one of the global clock (GCK) input pins (pin 23 or pin 27)?
Done . . . Moved to pin 27

Once we have the initial design working, one additional feature I would like to add is a split EEPROM / RAM configuration, so that:
- ROM 0 (&0000-&3FFF) is EEPROM
- ROM 1 (&0000-&35FF is EEPROM, &3600-&3FFF is RAM).
This would then allows the &E00 MMFS to work perfectly in ROM 1.

Which IC socket were you thinking of using for RAM? ROM 13 or ROM0/2? Still have enough room for another jumper :D

I'm adding an nOE net to ROM 13 - Still to do so don't know what pin it will go to?
New AP5 3D.JPG

AP5 Schematics 11-04-17.PDF
(753.39 KiB) Downloaded 17 times


Dave H :D
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Re: P.R.E.S. AP5 - Original and Re-Design

Postby daveejhitchins » Tue Apr 11, 2017 5:20 pm

Updated Schematic with the nOE for ROM 13 added in place of Gnd.

AP5 Schematics 11-04-17.PDF
(754.29 KiB) Downloaded 15 times


Dave H :D
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Re: P.R.E.S. AP5 - Original and Re-Design

Postby hoglet » Tue Apr 11, 2017 5:56 pm

daveejhitchins wrote:All I meant was the direction of the little red arrow on pin 74 is wrong. It's showing this pin as an output, and it's really an input I think.
BR/nW is an output to the Tube connector, 1MHz BUS connector, ROM13 and the 6522. Just a Buffered R/nW.

We are talking at cross purposes here :lol:

All I meant was the direction of the little red arrow on signal 1MHZNMI is wrong. It's showing this pin as an output, and it's really an input I think. This is purely cosmetic!

daveejhitchins wrote:
Once we have the initial design working, one additional feature I would like to add is a split EEPROM / RAM configuration, so that:
- ROM 0 (&0000-&3FFF) is EEPROM
- ROM 1 (&0000-&35FF is EEPROM, &3600-&3FFF is RAM).
This would then allows the &E00 MMFS to work perfectly in ROM 1.

Which IC socket were you thinking of using for RAM? ROM 13 or ROM0/2? Still have enough room for another jumper :D

I was thinking in this configuration the ROM0/2 would be the RAM.

The VHDL and UCF files are now consistent with the most recent 11-04-17 schematic:
https://github.com/hoglet67/ElectronAP5

Can you check a couple more things.

1. On the most recent 11-04-17 schematic, S1-RnW and S2-RnW seem to have been swapped where they connect to the two ROMs.

2. Does BRnW need to be gated with Phi0 by CPLD? If it's driving RAM in ROM13 then I think it should be gated, but then that will cause problems when it drives the Tube and 1MHz Bus. Could this signal be split?

Dave

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Re: P.R.E.S. AP5 - Original and Re-Design

Postby daveejhitchins » Tue Apr 11, 2017 6:20 pm

It's showing this pin as an output, and it's really an input I think.
The little red arrow is pointing the right way as pin 74 is outputting Buffered R/nW :D

I was thinking in this configuration the ROM0/2 would be the RAM.
You'll need to ensure the locking action is enabled for the accesses to the EEPROM and disabled when accessing the RAM! If you hadn't thought of that yet? I'll need to add that extra Jumper to indicate this particular set-up.


1. On the most recent 11-04-17 schematic, S1-RnW and S2-RnW seem to have been swapped where they connect to the two ROMs.
Arbitrary names! Would you prefer them the other way around? If I did change them I'd prefer to also swap the pins on the PLD, to keep the tracking the same.

2. Does BRnW need to be gated with Phi0 by CPLD? If it's driving RAM in ROM13 then I think it should be gated, but then that will cause problems when it drives the Tube and 1MHz Bus. Could this signal be split?
Yes it does, I'll fix that.

Dave H :D
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Re: P.R.E.S. AP5 - Original and Re-Design

Postby hoglet » Tue Apr 11, 2017 7:00 pm

daveejhitchins wrote:It's showing this pin as an output, and it's really an input I think.
The little red arrow is pointing the right way as pin 74 is outputting Buffered R/nW :D

I'm talking about NMI1MHZ, nor BRnW.
daveejhitchins wrote:I was thinking in this configuration the ROM0/2 would be the RAM.
You'll need to ensure the locking action is enabled for the accesses to the EEPROM and disabled when accessing the RAM! If you hadn't thought of that yet? I'll need to add that extra Jumper to indicate this particular set-up.

The locking will be more complicated, but still doable I think. So yes please add the jumper.
daveejhitchins wrote:1. On the most recent 11-04-17 schematic, S1-RnW and S2-RnW seem to have been swapped where they connect to the two ROMs.
Arbitrary names! Would you prefer them the other way around? If I did change them I'd prefer to also swap the pins on the PLD, to keep the tracking the same.

They are arbitrary I agree, but you have OE1, CE1, WR2 on one ROM and OE2, CE2, WR1 on the other. It makes my OCD brain hurt!
daveejhitchins wrote:2. Does BRnW need to be gated with Phi0 by CPLD? If it's driving RAM in ROM13 then I think it should be gated, but then that will cause problems when it drives the Tube and 1MHz Bus. Could this signal be split?
Yes it does, I'll fix that.

Great.

I'll wait for the next (final?) schematic instalment.

Dave

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Re: P.R.E.S. AP5 - Original and Re-Design

Postby daveejhitchins » Wed Apr 12, 2017 7:20 am

I'm talking about NMI1MHZ, nor BRnW.
Tut! Why didn't you say . . . :roll: :lol: I'll fix that - Glad we've got that sorted out :D

They are arbitrary I agree, but you have OE1, CE1, WR2 on one ROM and OE2, CE2, WR1 on the other. It makes my OCD brain hurt!
No problem . . .

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Re: P.R.E.S. AP5 - Original and Re-Design

Postby daveejhitchins » Wed Apr 12, 2017 11:12 am

Updated Schematic with all known changes. Note: Some PLD pins have been swapped!

J5 added as MMC Mode.

AP5 Schematics 12-04-17.PDF
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Re: P.R.E.S. AP5 - Original and Re-Design

Postby hoglet » Wed Apr 12, 2017 11:50 am

Hi Dave,
daveejhitchins wrote:Updated Schematic with the nOE for ROM 13 added in place of Gnd.

AP5 Schematics 11-04-17.PDF

I've updated the VHDL amd UCF files to track these changes:
https://github.com/hoglet67/ElectronAP5

The bad news is that as soon as a started trying to implement the "MMC" mode, I realized that to switch between EEPROM/RAM at &3600 within a ROM slot the CPLD logic needs to see A(8)..A(13). #-o

There are plenty of spare I/Os on the CPLD, but I suspect that connecting six additional address lines is not viable from a routing perspective.

What do you think? [-o<

Dave

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Re: P.R.E.S. AP5 - Original and Re-Design

Postby daveejhitchins » Wed Apr 12, 2017 12:26 pm

hoglet wrote:The bad news is that as soon as a started trying to implement the "MMC" mode, I realized that to switch between EEPROM/RAM at &3600 within a ROM slot the CPLD logic needs to see A(8)..A(13). #-o

There are plenty of spare I/Os on the CPLD, but I suspect that connecting six additional address lines is not viable from a routing perspective.

What do you think? [-o<
I'll see what I can do this afternoon . . .

Dave H :D
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Re: P.R.E.S. AP5 - Original and Re-Design

Postby dp11 » Wed Apr 12, 2017 12:42 pm

I would be tempted to add the databus to the CPLD to give options in the future. You can then also remove one of the databus buffers if required.

I don't quite understand the IIC connector and how it is meant to work. If PA1 and PA7 are the IIC bus then the 4K7 resistors are a bit large if external 2K2 pull up are used.

It's worth terminating TCK with a 100R to ground.

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Re: P.R.E.S. AP5 - Original and Re-Design

Postby hoglet » Wed Apr 12, 2017 1:17 pm

dp11 wrote:I don't quite understand the IIC connector and how it is meant to work. If PA1 and PA7 are the IIC bus then the 4K7 resistors are a bit large if external 2K2 pull up are used.

That header is for connecting to a serial port to support UPURS.

Dave

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Re: P.R.E.S. AP5 - Original and Re-Design

Postby daveejhitchins » Wed Apr 12, 2017 1:32 pm

hoglet wrote:
dp11 wrote:I don't quite understand the IIC connector and how it is meant to work. If PA1 and PA7 are the IIC bus then the 4K7 resistors are a bit large if external 2K2 pull up are used.

That header is for connecting to a serial port to support UPURS.


It's actually to support MartinB's IIC project :D see here.

Looks like I can get the extra address lines in :D

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Re: P.R.E.S. AP5 - Original and Re-Design

Postby MartinB » Wed Apr 12, 2017 2:28 pm

As Dave (hoglet) suggests, the IIC connector does appear on the schematic to have been bespoked to UPURS with the signal conditioning being provided by the 4K7 resistors and the diodes. My I2C interface also uses 6522 connections but unlike UPURS which uses data lines only, for I2C I use one data line and one control line (PB0 & CB2) together with 5v and 0v but no external passive components because the internal 1K pull-ups in the 6522 provide suitable SDA and SCL bias.

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Re: P.R.E.S. AP5 - Original and Re-Design

Postby daveejhitchins » Wed Apr 12, 2017 4:40 pm

Schematic update . . . I've managed to connect all address lines and all data lines to the XC9572 - Just in case!

AP5 Schematics 12-04-17A.PDF
(761.81 KiB) Downloaded 24 times

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Re: P.R.E.S. AP5 - Original and Re-Design

Postby daveejhitchins » Wed Apr 12, 2017 5:09 pm

Manufacturing Files Attached - Would appreciate a check over, please!

PCB Manufacturing Pack AP5 - 12-04-17-1.zip
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Re: P.R.E.S. AP5 - Original and Re-Design

Postby hoglet » Wed Apr 12, 2017 5:42 pm

daveejhitchins wrote:Schematic update . . . I've managed to connect all address lines and all data lines to the XC9572 - Just in case!

AP5 Schematics 12-04-17A.PDF
Dave H :D

Excellent work there Dave, this is looking very good indeed.

I've updated the VHDL and UCF file to match.

The .UCF file needs triple checking against the pinout in the schematic:
https://github.com/hoglet67/ElectronAP5 ... ronAP5.ucf

The MMC Mode is now implemented, and I've added a simple read/write test register at &FCD7 so the data bus does something:
https://github.com/hoglet67/ElectronAP5 ... P5.vhd#L74

What program should I use to view the manufacturing files?

Dave

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Re: P.R.E.S. AP5 - Original and Re-Design

Postby daveejhitchins » Wed Apr 12, 2017 6:25 pm

I use ViewMate to check the Gerbers with the Drill files added. You can also view the ODB++ files too. These may be easier to load and view as they come as a complete package.

Note: You have to Import the above files. Import the Gerber files first. Select the next empty position (at the left hand side of the screen) then import the drill files.

If you Import the ODB++ files - When selecting the files - open the ODB++ folder (you'll need to extract the zip first) and drill down 1 level - then, at the bottom of the Import window, use the click option (sorry can't remember what it says!).

I'll check the Pin list.

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Re: P.R.E.S. AP5 - Original and Re-Design

Postby daveejhitchins » Wed Apr 12, 2017 6:58 pm

.UCF file checked:

You have A14 marked as on output - pin 93

that seems to be all.

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Re: P.R.E.S. AP5 - Original and Re-Design

Postby hoglet » Wed Apr 12, 2017 7:01 pm

daveejhitchins wrote:You have A14 marked as on output - pin 93

That's because it is a an output, driving A14 of ROM 1/3. :D

Dave

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Re: P.R.E.S. AP5 - Original and Re-Design

Postby daveejhitchins » Wed Apr 12, 2017 7:04 pm

hoglet wrote:That's because it is a an output, driving A14 of ROM 1/3. :D
That would be my schematics that have it marked wrongly #-o

I'll also change the Data lines to show bidirectional . . .

Dave H :D - - - Getting there - The Manufacturing files should be correct. DRC passes zero errors :D
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Re: P.R.E.S. AP5 - Original and Re-Design

Postby hoglet » Wed Apr 12, 2017 7:36 pm

Dave,

I've just been reviewing the schematics, and have a question: Are you planning to use an XC9572 or an XC9572XL?

If the XC9572, do you have a source for this, as it's very hard to find now. What speed grade?

If the XC9572XL, then that's basically a 3.3V part, with 5V tolerant I/Os. It needs a 3.3V power supply.

Dave

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Re: P.R.E.S. AP5 - Original and Re-Design

Postby daveejhitchins » Wed Apr 12, 2017 7:42 pm

hoglet wrote:I've just been reviewing the schematics, and have a question: Are you planning to use an XC9572 or an XC9572XL?
PM sent . . .

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Re: P.R.E.S. AP5 - Original and Re-Design

Postby dp11 » Wed Apr 12, 2017 9:17 pm

Hi Dave H,

Very minor comments. The decoupling capacitor loop area can be reduced for some of the ICs. e.g. I'd like to see an extra GND via just above pin 1 of ROM1/3 to improve the ground return for the decoupling cap. Similar for the 6522, IC2, IC4 .

IC2 silk label appears to have gone for a wonder :)

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Re: P.R.E.S. AP5 - Original and Re-Design

Postby daveejhitchins » Wed Apr 12, 2017 9:35 pm

dp11 wrote:Hi Dave H,

Very minor comments. The decoupling capacitor loop area can be reduced for some of the ICs. e.g. I'd like to see an extra GND via just above pin 1 of ROM1/3 to improve the ground return for the decoupling cap. Similar for the 6522, IC2, IC4 .

IC2 silk label appears to have gone for a wonder :)
Thanks for the feedback . . I'll add the extras and find IC2 - By the way . . . Have you seen my original? :D
AP5-2.jpg

Dave H :D
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Re: P.R.E.S. AP5 - Original and Re-Design

Postby daveejhitchins » Thu Apr 13, 2017 11:19 am

Final(?) update - I've added a 3V3 (optional) regulator in case I have to use the XC9572XL - I currently have stock of the XC9572 (5V) Part.

AP5 Schematics 13-04-17.PDF
(779.3 KiB) Downloaded 23 times
New AP5 3D.JPG
PCB Manufacturing Pack AP5 - 13-04-17.zip
(1.33 MiB) Downloaded 18 times


Dave H :D
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Re: P.R.E.S. AP5 - Original and Re-Design

Postby hoglet » Thu Apr 13, 2017 12:07 pm

That sir is definitely a thing of beauty =D> =D> =D>

I've added the report and jedec file for the latest CPLD build into github:
https://github.com/hoglet67/ElectronAP5/

Dave

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Re: P.R.E.S. AP5 - Original and Re-Design

Postby daveejhitchins » Thu Apr 13, 2017 12:09 pm

Now to order the prototype PCBs . . . and start the case design.

Dave H :D
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Re: P.R.E.S. AP5 - Original and Re-Design

Postby danielj » Thu Apr 13, 2017 1:05 pm

=D> =D> =D>

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Re: P.R.E.S. AP5 - Original and Re-Design

Postby danielj » Thu Apr 13, 2017 1:07 pm

Just a thought, could there be a break off tab on the right of the pcb to stabilise it if it's not cased?

D.

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Re: P.R.E.S. AP5 - Original and Re-Design

Postby daveejhitchins » Thu Apr 13, 2017 1:40 pm

Not cased* :shock: Daniel, how could you. [-X

5 x Prototypes ordered (FirstPCB.com) 5 days + UPS Delivery!

* maybe there could be a simple 'printed' stabiliser?

Dave H :D
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Products: ARA II, ABR, ATI, AP6, MGC, AP5 . . .
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