P.R.E.S. AP5 - Original and Re-Design

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daveejhitchins
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P.R.E.S. AP5 - Original and Re-Design

Postby daveejhitchins » Mon Aug 18, 2014 9:36 am

The recent Mini-HackFest (15/16 Aug 2014) gave me time to complete the schematics, from reverse engineering, of the Issue 1 AP5 PCB. The schematics (pdf and jpg format) are attached. If someone could carry out a sanity check. I would be most grateful.
AP5Schematics.jpg
Schematic of the original AP5


The idea was also to find out why the 1MHz Bus cartridge wasn't working with the DataCentre. I had hoped to accomplish this by confirming that the data centre worked, as suggested by Mark (RetroClinic), with the AP5. As I'd just finalised a refurbishment, of said AP5, I wasn't expecting any problems. However, Murphy struck! It didn't work!

The RamFS, part of the DataCentre, checks for the presence of the hardware by writing to &FCFF and checking that the same data can be read back. A simple BASIC program to write to this address. plus &FDxx, showed that there were problems. It was near, but not near enough :?

So, my first job is to connect it to my Master 128 and make sure the DataCentre is working OK. Then to take some screen-shots of the timing of the data transfer, in relation to the 1MHz Bus 1MHz clock signal. Once I have that then I can connect the AP5, taking similar screen-shot for a comparison.

More later. . .
*********************************
Please check your status and advise if incorrect.

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#   Name              Forum Name        Built  Kit  Case
1   John Davis                            2           ?
2   Mark Kinsey        1024MAK            1           1
3   John Simpson       JMS2                     1     1
4   Stephen Preston    paradroid90              1     1
5   Richard Toohey     richardtoohey      1           1   
6   Bas Gialopsos      TheCorfiot               1     1
7   Howard Watson      Wookie             ?     ?     ?
8   Ray Harper         rharper            2           2
9   Graeme Gregory     XorA               1           ?   
10  Graham Campbell    fatbob_gb                1     1
11  Daniel Jameson     danielj                  1     1
12  Nicholas Walker    dixiestoat         1           1
13  Jon Conyers        JonC               1           1
14  Duncan Reed        Elminster                1     1
15  Nick Balmer        Elk Towers         1           1
16  Stuart Johns       aerworuld          1           1
17  Alex Wilson        sixdog             2           ?
18  Neil Beadle                           1           ?
19  Matthew Nicholson  mattyj             2           ?   
20  Mark Smith                            1           ?   
21  Marcus             marcusjambler      1           1
22  Scott Goodwin      ssgoodwin          1           1
23  Martin Barr        MartinB            ?      ?    1
24  Chris Gransden     grannyg            1           1
25  Ian Tomlinson      tomlinson          1           1
26  Michael Sadler                        ?      ?    ?
27                     stevebubs          ?      ?    ?
28  Colin McDougall    CMcDougle                 1
29  1987akaTheMoneyPit                           1    1


Dave H :D
AP5SchematicsPDF.pdf.zip
Schematic of the original AP5
(179.07 KiB) Downloaded 143 times
Last edited by daveejhitchins on Fri Sep 01, 2017 7:53 am, edited 4 times in total.
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Re: P.R.E.S. AP5 - Original and Re-Design

Postby aerworuld » Mon Aug 18, 2014 9:58 am

Excellent work Mr H :D

=D> =D> =D>

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Re: P.R.E.S. AP5 - Original and Re-Design

Postby danielj » Mon Aug 18, 2014 10:07 am

Dave, is the address coding letting the right ones through? The AP5 was rather "illiberal" to say the least...

If that's Dave M's AP5, I've definitely had it working with a datacentre. Only problem is because of the "tight" address ranges you can't use the IDE HDD interface. Also IIRC it stops you using the beebsid :(

d.

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Re: P.R.E.S. AP5 - Original and Re-Design

Postby daveejhitchins » Mon Aug 18, 2014 1:20 pm

danielj wrote:Dave, is the address coding letting the right ones through? The AP5 was rather "illiberal" to say the least...Daniel, &FCA0>AF : &FCC0>CF : &FCF0>FF are catered for . . .
I did check to see if there was an output on pins 10 and 12 of the connector.

danielj wrote:If that's Dave M's AP5, I've definitely had it working with a datacentre.
Hmmm- He has more than one!! This one was very uncared for, shall we say!
danielj wrote:Only problem is because of the "tight" address ranges you can't use the IDE HDD interface. Also IIRC it stops you using the beebsid :(
Hmm! I'm not sure why we limited the access to FRED . . . Reasons lost in time I suspect. Peter Garrett did most of that design (that's a mean thing - blaming someone else :oops: ). The new model could fix all that :D

Dave H :D
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Re: P.R.E.S. AP5 - Original and Re-Design

Postby daveejhitchins » Tue Aug 19, 2014 10:22 pm

OK, AP5 sorted . . . Very fine short on the 1MHz connector. Now working with DataCentre :D

Working on the Cartridge version now. Almost sure the problem is with the 1mHz clock - but will need to have a ponder.

Dave H :D

p.s. anyone found anomalies with the schematic - I know there's a graphical error, however, that's fixed now.
Parts: UM6502CE, GAL22V10D, GAL16V8D, AS6C62256A, TC514400AZ, WD1772, R6522, TMS27C512, AT28C256
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Re: P.R.E.S. AP5 - Original and Re-Design

Postby richardtoohey » Tue Aug 19, 2014 11:04 pm

=D>

Can't help with the schematic, but watching the progress! :D

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Re: P.R.E.S. AP5 - Original and Re-Design

Postby 1024MAK » Tue Aug 19, 2014 11:14 pm

Thoughts so far...

Is IC9 a 74LS138?

Is there any reason that non-buffered address lines (A0 to A6) and R/nW are used for the Tube connector? Seems a bit silly when you already have these signals buffered for the 1MHz bus...

Can't see a type number for IC12 or IC14.
Can't see a type number for TR1.

Is it worth while supporting 27C256 EPROMs in the ROM sockets?

Is it worthwhile using the currently unused 6522 PA0 to PA7 and CA1, CA2 lines to form a second user port (only need a 100k pull up for CA1 and a 20 way IDC plug).

Mark
Last edited by 1024MAK on Wed Aug 20, 2014 9:07 am, edited 1 time in total.
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Re: P.R.E.S. AP5 - Original and Re-Design

Postby daveejhitchins » Wed Aug 20, 2014 7:07 am

1024MAK wrote:Is IC9 a 74LS138?
I've no idea why the range of FRED is limited in this way. It seems we were consistent, though, as the same limitations are applied to the cartridge version!

1024MAK wrote:Is there any reason that non-buffered address lines (A0 to A6) and R/nW are used for the Tube connector? Seams a bit silly when you already have these signals buffered for the 1MHz bus...
Apart from the Tube being faster - more critical? And it's buffered in the Plus 1 ???

1024MAK wrote:Can't see a type number for IC12 or IC14.
Can't see a type number for TR1.
Will fix this, thanks.

1024MAK wrote:Is it worth while supporting 27C256 EPROMs in the ROM sockets?
In the new version - absolutely - including anything specific for the 28C256.

1024MAK wrote:Is it worthwhile using the currently unused 6522 PA0 to PA7 and CA1, CA2 lines to form a second user port (only need a 100k pull up for CA1 and a 20 way IDC plug).
If room for it can be found . . .

Thanks Mark.

Dave H :D
Parts: UM6502CE, GAL22V10D, GAL16V8D, AS6C62256A, TC514400AZ, WD1772, R6522, TMS27C512, AT28C256
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Re: P.R.E.S. AP5 - Original and Re-Design

Postby danielj » Wed Aug 20, 2014 7:46 am

It's because Acorn said that loads of ranges in FRED were "reserved" - e.g. for an Elk Econet etc.

I worked out that you could allow &FC00-&FC6F and &FFF0-&FFFF through without upsetting anything that anyone was likely to have other than the AQMR (which clashes with the data centre anyway).

The serial controller's meant to live at 60-6F so you could, I guess give the option of restricting that and Stuart can still use his modem whilst having the AP5 plugged in :D

You could also let 90-9F through, I think that's for a sound/speech expansion rather than anything internal?

Perhaps the option to configure which ranges you let through with some DIPs would be nice...

d.

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Re: P.R.E.S. AP5 - Original and Re-Design

Postby daveejhitchins » Wed Aug 20, 2014 8:42 am

danielj wrote:It's because Acorn said that loads of ranges in FRED were "reserved" - e.g. for an Elk Econet etc.

Perhaps the option to configure which ranges you let through with some DIPs would be nice...
Good plan Daniel . . .

Dave H :D
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Re: P.R.E.S. AP5 - Original and Re-Design

Postby 1024MAK » Wed Aug 20, 2014 9:06 am

daveejhitchins wrote:
1024MAK wrote:Is there any reason that non-buffered address lines (A0 to A6) and R/nW are used for the Tube connector? Seems a bit silly when you already have these signals buffered for the 1MHz bus...
Apart from the Tube being faster - more critical? And it's buffered in the Plus 1 ???
Err, no address, data or control bus buffering in the Acorn Plus 1. The Acorn Plus 3 has buffering, maybe that's what you were thinking of...
The circuit diagram of the Plus 1 is available somewhere on the forum, as Phill (Prime) has redrawn it.

Mark
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Re: P.R.E.S. AP5 - Original and Re-Design

Postby daveejhitchins » Wed Aug 20, 2014 12:18 pm

Ah, hence the ??? Didn't bother to look :?

All will be fixed in the NEW design :wink: [-o<

Dave H :D
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Re: P.R.E.S. AP5 - Original and Re-Design

Postby daveejhitchins » Sun Sep 28, 2014 10:30 am

Update . . . I'm starting to gather all the changes together for the new version of the Plus 5.

(1) Full Address and Data buffering for all the interfaces.
(2) Extra socket for a second User Port <- To fully utilise the 6522. Will be placed in parallel with existing socket.
(3) Full access to Page &FC <- Unless someone has some misgivings about this?
(4) More use of PLDs <- To reduce the chip count.
(5) Include ABR type write protection <- For *
(6) To work with RAM* and/or EEPROM*
(7) Optional battery back-up circuit <- With ability to link-out if not required.
(8) Ability to link-out ROM 13 <- In case another interface need this slot.

Have I missed anything that may be useful?

Dave H :D
Parts: UM6502CE, GAL22V10D, GAL16V8D, AS6C62256A, TC514400AZ, WD1772, R6522, TMS27C512, AT28C256
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Re: P.R.E.S. AP5 - Original and Re-Design

Postby aerworuld » Thu Oct 02, 2014 8:51 pm

1 mhz bus part is happy with Music 500 isnt it Dave? Im putting one of these AP5's on my chrimbo wish list that im going to leave around for the wife to find lol

Good luck with the board! ;)

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Re: P.R.E.S. AP5 - Original and Re-Design

Postby richardtoohey » Thu Oct 02, 2014 9:26 pm

aerworuld wrote:my chrimbo wish list that im going to leave around for the wife to find lol
Oh, no, no, no! [-X :shock:

That leaves too much to chance. You need to buy one, and then leave it next to some wrapping paper (including gift tag with your name on), sellotape, etc.

:lol:

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Re: P.R.E.S. AP5 - Original and Re-Design

Postby aerworuld » Fri Oct 03, 2014 5:00 am

richardtoohey wrote:
aerworuld wrote:my chrimbo wish list that im going to leave around for the wife to find lol
Oh, no, no, no! [-X :shock:

That leaves too much to chance. You need to buy one, and then leave it next to some wrapping paper (including gift tag with your name on), sellotape, etc.

:lol:


Excellent plan Richard! Im sensing you have tested this method yourself ;-)

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Re: P.R.E.S. AP5 - Original and Re-Design

Postby richardtoohey » Fri Oct 03, 2014 5:04 am

Good Lord, no! This is just a step in your journey, little grasshopper!

I am a Grand Master - I wrap it as well and place it under the tree - just swing it past her long enough for her squiggle on the card, to make it look like she did something! :lol:

But at least Santa brings me what I want! :D I mean, Christmas is all about me getting presents that I want, isn't it? :-k

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Re: P.R.E.S. AP5 - Original and Re-Design

Postby danielj » Fri Oct 03, 2014 9:08 am

Dave, I'd be careful about letting everything through - won't the buffering cause issues with things that aren't "on the 1MHz bus" if it's on the whole time? e.g. plus 3/ap3/4 etc, etc?

d.

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Re: P.R.E.S. AP5 - Original and Re-Design

Postby daveejhitchins » Fri Oct 03, 2014 7:10 pm

danielj wrote:Dave, I'd be careful about letting everything through - won't the buffering cause issues with things that aren't "on the 1MHz bus" if it's on the whole time? e.g. plus 3/ap3/4 etc, etc?

d.
OK, point taken . . .When I have a look at Page &FC I'll post a list of what I think we need, however, in the mean time, if anyone has thoughts . . . please let me know - Ta :D

Dave H :D
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Re: P.R.E.S. AP5 - Original and Re-Design

Postby 1024MAK » Fri Oct 03, 2014 10:54 pm

Hmm, we need an agreed memory map of page &FC showing wanted 1MHz bus ranges, blocked 1MHz bus ranges, and switchable/selectable 1MHz bus ranges. Also we need to sort out how a user would enable/disable these switchable/selectable 1MHz bus ranges... Maybe DIP switches :-k

Mark
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Re: P.R.E.S. AP5 - Original and Re-Design

Postby danielj » Sat Oct 04, 2014 5:39 am

When I looked at this I decided blocking &FC70-&FCEF was the most sensible option:

viewtopic.php?p=43744#p43744

But I was using discrete logic and doing anything fancy would have increased the chip count ridiculously.

Possibly extend down to &FC60 to allow the Serial Port? I definitely think the most useful thing would be a set of DIP switches to allow flexibility in paging in different ranges. You're always going to need to block out the 6522 and the TUBE (&B0-&BF and &E0-&EF), and the Plus 1 (&70-&73). Most people will also need &C0-&CF blocked out too for the FDD... The rest should probably be a bit more flexible.

That's my two pennies anyway. :D

d.

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Re: P.R.E.S. AP5 - Original and Re-Design

Postby daveejhitchins » Sat Oct 04, 2014 8:05 am

Thanks, Daniel.

Dave H :D
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Re: P.R.E.S. AP5 - Original and Re-Design

Postby daveejhitchins » Thu Oct 09, 2014 10:54 am

Update . . .

(1) Full Address and Data buffering for all the interfaces.
     Done. (Added buffered address' to the Tube connector.)
(2) Extra socket for a second User Port.
      Done.
(3) Full access to Page &FC -> See below, still 'open'
(4) More use of PLDs <- To reduce the chip count.
(5) Include ABR type write protection <- For *
(6) To work with RAM* and/or EEPROM*
(7) Optional battery back-up circuit <- With ability to link-out if not required.
(8) Ability to link-out ROM 13 <- In case another interface needs this slot.
Done.
(9) Schematic now has all ICs labeled.

Here is a list of FRED usage: (Is it correct?)

Code: Select all

&FC00 to &FC0F    Test hardware
&FC10 to &FC13    TELETEXT
&FC14 to &FC1F    PRESTEL
&FC20 to &FC27    IEEE 488 interface
&FC28 to &FC2F    ECONET
&FC30 to &FC3F    CAMBRIDGE RING interface
&FC40 to &FC47    WINCHESTER DISC interface
&FC48 to &FC5F    Reserved for Acorn expansions
&FC60 to &FC6F    6850 ACIA
&FC70             A to D converter
&FC71             CENTRONICS parallel interface
&FC72             Status register
                  BSY ADC FB2 FB1 X X X X
                  Where   BSY = printer busy
                        ADC = A to D conversion end
                        FB1 = Fire button 1
                        FB2 = Fire button 2
                        X= undefined
&FC73 to &FC7F    Reserved for Acorn expansions
&FC80 to &FC8F   *Test hardware
&FC90 to &FC9F    Sound and speech
&FCA0 to &FCAF   *Reserved for Acorn expansions
&FCB0 to &FCBF   *6522 VIA/Real time clock
&FCC0 to &FCCF    Floppy disc controller
&FCD0 to &FCDF    USER applications
                        AP7:
                        &FCD8 Unlock Register - Low Bank
                        &FCD9 Lock Register - Low Bank
                        &FCDA Unlock Register - High Bank
                        &FCDB Lock Register - High Bank
                        ABR:
                        &FCDC Unlock Register - Slots 0&2
                        &FCDD Lock Register - Slots 0&2
                        &FCDE Unlock Register - Slots 1&3
                        &FCDF Lock Register - Slots 1&3
&FCE0 to &FCEF   *The TUBE
&FCF0 to &FCFE   *USER applications
                        DataCentre:
                        &FCF8 VNC1L Data Port
                        &FCF9 VNC1L Control Port
                        &FCFA NVRAM Data Port
                        &FCFB NVRAM Data Direction Register
                        &FCFC NVRAM Clock  *CLASH WITH AQR*
                        &FCFD NVRAM Write Protect  *CLASH WITH AQR*
                        &FCFE Page RAM MSB  *CLASH WITH AQR*
                        AQR:
                        &FCFC Page Register  *CLASH WITH DataCentre*
                        &FCFD Unlock Register  *CLASH WITH DataCentre*
                        &FCFE Lock Register  *CLASH WITH DataCentre*
&FCFF               Paging register for JIM
                        DataCentre:
                        &FCFF Paged RAM LSB
I've preceded the pages, I think we can use, with a * (5!) -> Note: I'm currently not selecting any pages below &FC80, due to hardware addressing. Are there any 'useful' pages below here?

1024MAK wrote:(only need a 100k pull up for CA1 and a 20 way IDC plug)
Mark, why?
Schematic 09-10-14.JPG
AP5 Schematics 09-10-14.zip
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Dave H :D
Parts: UM6502CE, GAL22V10D, GAL16V8D, AS6C62256A, TC514400AZ, WD1772, R6522, TMS27C512, AT28C256
Products: ARA II, ABR, ATI, AP6, MGC, AP5 . . .
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Re: P.R.E.S. AP5 - Original and Re-Design

Postby danielj » Thu Oct 09, 2014 11:07 am

daveejhitchins wrote:I've preceded the pages, I think we can use, with a * (5!) -> Note: I'm currently not selecting any pages below &FC80, due to hardware addressing. Are there any 'useful' pages below here?


Great work! BeebSID lives at &FC20-&FC3F so that needs to be open.

d.

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1024MAK
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Re: P.R.E.S. AP5 - Original and Re-Design

Postby 1024MAK » Thu Oct 09, 2014 11:35 am

daveejhitchins wrote:
1024MAK wrote:(only need a 100k pull up for CA1 and a 20 way IDC plug)
Mark, why?

CA1 is a high impedance input only pin, so to prevent it floating, it is wise to add a pull-up. By using 100k, this should not affect any user circuitry that wants to pull it low.

:arrow: See this thread.

Looking good there Dave H :D =D>

Mark
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1024MAK
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Re: P.R.E.S. AP5 - Original and Re-Design

Postby 1024MAK » Thu Oct 09, 2014 11:36 am

danielj wrote:Great work! BeebSID lives at &FC20-&FC3F so that needs to be open.
Would be fun to have an Elk driving the BeebSID 8)

Mark
For a "Complete BBC Games Archive" visit www.bbcmicro.co.uk NOW!
BeebWiki‬ - for answers to many questions...

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Re: P.R.E.S. AP5 - Original and Re-Design

Postby danielj » Thu Oct 09, 2014 12:01 pm


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aerworuld
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Re: P.R.E.S. AP5 - Original and Re-Design

Postby aerworuld » Fri Mar 06, 2015 7:56 pm

Hi Dave,

Any joy with the AP5 rebirth?

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TheCorfiot
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Re: P.R.E.S. AP5 - Original and Re-Design

Postby TheCorfiot » Fri Mar 06, 2015 9:47 pm

Cmon Dave, i want a dozen at least lol

;)

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Re: P.R.E.S. AP5 - Original and Re-Design

Postby daveejhitchins » Sat Mar 07, 2015 11:19 pm

I think I'm at the point of having a final schematic. I'll get it posted here ASAP.

Dave H :D
Parts: UM6502CE, GAL22V10D, GAL16V8D, AS6C62256A, TC514400AZ, WD1772, R6522, TMS27C512, AT28C256
Products: ARA II, ABR, ATI, AP6, MGC, AP5 . . .
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