Also useful reading (from 8bs.com/inbbc/html):
The 1MHz system clock is actually generated by externally dividing the 2MHz signal by 2 using a D-flip-flop (half of IC34); the 1MHz signal out of the video ULA is only used for driving ICs 5 and 15. Two more D-type flip-flops (IC30) and an OR gate are used to generate the 2MHz clock for the CPU, which has a specific waveform requirement. Requests for a 1MHz processor cycle from the address decoding are fed via an inverter (1/6th of IC33) to a D-flip-flop (half of IC31) which latches the request for a 1MHz cycle. At the appropriate time, as governed by the 2MHz clock, one of the 2MHz clock cycles is masked off by a D-flip-flop (half of IC34). When this happens the D flip-flop that latched the request is cleared, to re-enable the 2MHz CPU clock at the next appropriate clock phase.
(I can't guarantee all the following is correct, but it made sense to me as I wrote it.)
On that basis, when the system is reset, /RST on IC34 pin 4 presets that flip-flop, so output /Q on pin 6 is low. This in turn presets IC31 on pin 10, so IC31 pin 8 (/Q) is also low. The output of IC33 (pin 2) will be high unless a request for 1MHz operation comes through, so (through IC29) the D input to IC34 (pin 2) will be high.IC34 pin 6 will remain low for the time being, so the output of IC29 (feeding the CPU's PHI IN) will only depend on the 2MHz clock coming from IC30.
This state of affairs will change when a request for 1MHz is made, and IC23 pin 8 goes from low to high. IC33 and IC29 will invert immediately (except gate delays) such that D input to IC34 (pin 2) is now low. When IC34 pin 3 next sees a rising clock pulse (from the 2MHz clock on IC30 pin 5) this change will propagate through to IC34 pin 6, which will go high. It will remain high, so the CPU's PHI IN won't drop low at the next down transition of the 2MHz clock.
IC34 pin 6 also controls the preset for IC31 (through pin 10). When this goes high, the state of the flip-flip can change. It is clocked by the 1MHzE clock signal, and the Data input is from IC33 pin 2 (which is already low). When 1MHzE rises and IC34 flips, both of IC29's inputs (pins 9 and 10) will be low, so the data input for IC34 (pin 2) will be low. It isn't long since the last rising edge of the 2MHz clock, so this won't happen for a while.
Let's go back and look at the other branch coming out of IC23 pin 8: IC28. To summarise this gate, the output on pin 8 will be high unless PHI1, 1MHzE, and IC23 pin 8 are ALL high, at which point it will output low. So when IC28 goes high, IC 23 won't necessarily change at once. (PHI1 will only be high when the CPU's PHI IN is low.) The change will only happen when it's correctly synchronised with the other clock signals. At this point, IC30 pin 1 will reset the output of the flip-flop, and Q (pin 5) will fall low. Note that this is also the clock input for IC34 on pin 3, so we're almost ready for a rising clock edge there!
IC23's output will only stay low until the 1MHzE input changes again. At this point, the CLEAR on IC30 pin 1 will be removed, and its Q on pin 5 will start showing a 2MHz clock signal again. (In the meantime we'll have missed one clock pulse, so dropping to 1MHz.) When that clock signal arrives, it advances IC34 's low on pin 2 through to pin 5 (/Q), presetting IC31's flip-flop, with its /Q going low.
If the request for a 1MHz clock through IC28 remains, D (pin 2) on IC34 will remain high because of IC33, and we'll clear IC30 again one clock cycle later, continuing to drop half the clock pulses (and lengthen some with IC34 to make a balanced 1MHz clock signal).
Hopefully this will help you compare your Beeb's behaviour to what should be happening.