Open Source Logic Analyzer Experiments

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hoglet
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Re: Open Source Logic Analyzer Experiments

Postby hoglet » Mon Nov 20, 2017 12:03 pm

Part 6 has been posted here

In summary, we can now debug by connecting the Logic Analyzer only to the Tube connector:
IMG_1136.JPG

This is using the cheap (£13.44 delivered) logic analyzer, from here.

Dave

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fordp
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Re: Open Source Logic Analyzer Experiments

Postby fordp » Mon Nov 20, 2017 9:51 pm

I wonder if a Raspberry Pi cobbler would work to connect the tube to the Logic analyser?
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Re: Open Source Logic Analyzer Experiments

Postby dp11 » Mon Nov 20, 2017 10:01 pm

The brain has already a plan for this and something else.

For the LA how would you like to interact with it ?

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hoglet
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Re: Open Source Logic Analyzer Experiments

Postby hoglet » Mon Nov 20, 2017 10:04 pm

fordp wrote:I wonder if a Raspberry Pi cobbler would work to connect the tube to the Logic analyser?

I think possibly not, because it looks like some of the power pins (e.g. the two +5V pins) are connected together.

Do you have one?
Last edited by hoglet on Mon Nov 20, 2017 10:11 pm, edited 1 time in total.

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Re: Open Source Logic Analyzer Experiments

Postby fordp » Mon Nov 20, 2017 10:09 pm

I do and I thought some pins may be connected together. I have one of the Logic analyser boards too. I also have too many projects on the go :(
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Re: Open Source Logic Analyzer Experiments

Postby stevei2791 » Tue Nov 21, 2017 9:03 pm

Maybe for a master machine version, it would be easier to create a bare cartridge with the required lines straight onto the board, or into sockets on the cartridge so the cypress board can be mated to the cartridge. Would probably have to be careful with the clearance for the board and the slot covers.

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Re: Open Source Logic Analyzer Experiments

Postby paulb » Wed Nov 22, 2017 3:24 pm

stevei2791 wrote:Maybe for a master machine version, it would be easier to create a bare cartridge with the required lines straight onto the board, or into sockets on the cartridge so the cypress board can be mated to the cartridge. Would probably have to be careful with the clearance for the board and the slot covers.


An Electron version could use the cartridge interface, too. And there's always the Electron and Master Compact expansion connectors, although I haven't really looked at the latter in any depth, but I guess that it is easily good enough for this hardware's requirements.

Also, I have to say, if I haven't already, that this is a great project with a nice trail of documentation. One day I'll have to play with bus monitoring!

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Re: Open Source Logic Analyzer Experiments

Postby myelin » Wed Nov 22, 2017 6:36 pm

paulb wrote:An Electron version could use the cartridge interface, too. And there's always the Electron and Master Compact expansion connectors, although I haven't really looked at the latter in any depth, but I guess that it is easily good enough for this hardware's requirements.


The cartridge interface should bring out all the required signals here, even READY, although that's not necessary as the Electron uses clock-stretching during slow accesses, like the Model B (although it slows down for main memory accesses, not just the 1MHz Bus addresses).

Wiring up a Cypress FX2 board to one of your Elk cartridge breakout boards should be pretty trivial in fact! I was going to try it with my CPU socket expansion, but I think the cartridge route is better actually...
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Re: Open Source Logic Analyzer Experiments

Postby fordp » Wed Nov 22, 2017 11:15 pm

Maybe a PCB with both a tube connector and a cartridge slot can be made to allow Beeb, Master and Electron to be monitored?
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Re: Open Source Logic Analyzer Experiments

Postby myelin » Wed Nov 22, 2017 11:57 pm

fordp wrote:Maybe a PCB with both a tube connector and a cartridge slot can be made to allow Beeb, Master and Electron to be monitored?


Good thinking. It would look a bit odd but would work well! Cartridge connector on one side, Tube cable header on the other, and header for the lcsoft FX2 board in between. I'm going to be making a PCB order in a few days, so I'll see about whipping up one of these once I get a chance to measure the lcsoft board to figure out exact sizing.

Dave, is this still the correct pinout -- D0-7 to PB0-7, RnW to PD0, 2MHzE to PD3, and /RST to PD6?

Code: Select all

 Tube    lcsoft board
------   ------------
Pin  1    (0V) -> GND
Pin  2   (RnW) -> PD0
Pin  4 (2MHzE) -> PD3
Pin 10  (NRST) -> PD6
Pin 11    (0V) -> GND
Pin 12    (D0) -> PB0
Pin 14    (D1) -> PB1
Pin 16    (D2) -> PB2
Pin 18    (D3) -> PB3
Pin 20    (D4) -> PB4
Pin 22    (D5) -> PB5
Pin 24    (D6) -> PB6
Pin 26    (D7) -> PB7


A bunch more signals are available on the Electron, so I figure I may as well wire as many as I can to PD*. READY, /IRQ, and /NMI are obvious ones to do. Otherwise it's just address lines, which aren't that useful here, given that A14 and A15 are missing. I guess I'll pull in A0, seeing as it's also on the Tube connector.
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Re: Open Source Logic Analyzer Experiments

Postby hoglet » Thu Nov 23, 2017 8:17 am

myelin wrote:Dave, is this still the correct pinout -- D0-7 to PB0-7, RnW to PD0, 2MHzE to PD3, and /RST to PD6?
...
A bunch more signals are available on the Electron, so I figure I may as well wire as many as I can to PD*. READY, /IRQ, and /NMI are obvious ones to do. Otherwise it's just address lines, which aren't that useful here, given that A14 and A15 are missing. I guess I'll pull in A0, seeing as it's also on the Tube connector.

Yes, and I would be inclined to wire the additional PD pins as follows:

Code: Select all

 Tube    lcsoft board        Cartridge
------   ------------    ----------------
Pin  1    (0V) -> GND <- (0V)    Pin A22
Pin  2   (RnW) -> PD0 <- (RnW)   Pin A4 (Elk)/Pin A11 (Master)
                  PD1 <- (Sync)  via wire/test clip
                  PD2 <- (Rdy)   Pin A11 (Elk)/via wire/test Clip (Master)
Pin  4 (2MHzE) -> PD3 <- (Phi2)  Pin A8
                  PD4 <- (NIRQ)  Pin A13
                  PD5 <- (NNMI)  Pin A12   
Pin 10  (NRST) -> PD6 <- (NRST)  Pin A3
Pin 11    (0V) -> GND <- (0V)    Pin B22
Pin 12    (D0) -> PB0 <- (D0)    Pin B19
Pin 14    (D1) -> PB1 <- (D1)    Pin B21
Pin 16    (D2) -> PB2 <- (D2)    Pin B20
Pin 18    (D3) -> PB3 <- (D3)    Pin B3
Pin 20    (D4) -> PB4 <- (D4)    Pin B9
Pin 22    (D5) -> PB5 <- (D5)    Pin B8
Pin 24    (D6) -> PB6 <- (D6)    Pin B7
Pin 26    (D7) -> PB7 <- (D7)    Pin B6
Pin 28    (A0) -> PD7 <- (A0)    Pin B18

Note that the cartridge pin for RnW differs between the Elk and Master.

I can also confirm that (as expected) the external Tube on the Master doesn't work (it's value is FF most of the time).

I'm having a few problems correctly sampling signals on the Master when running code out of RAM:
https://github.com/hoglet67/6502Decoder/issues/1

More investigation is needed here.

Dave

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Re: Open Source Logic Analyzer Experiments

Postby fordp » Thu Nov 23, 2017 1:03 pm

myelin wrote:
fordp wrote:Maybe a PCB with both a tube connector and a cartridge slot can be made to allow Beeb, Master and Electron to be monitored?


Good thinking. It would look a bit odd but would work well! Cartridge connector on one side, Tube cable header on the other, and header for the lcsoft FX2 board in between. I'm going to be making a PCB order in a few days, so I'll see about whipping up one of these once I get a chance to measure the lcsoft board to figure out exact sizing.

Dave, is this still the correct pinout -- D0-7 to PB0-7, RnW to PD0, 2MHzE to PD3, and /RST to PD6?

Code: Select all

 Tube    lcsoft board
------   ------------
Pin  1    (0V) -> GND
Pin  2   (RnW) -> PD0
Pin  4 (2MHzE) -> PD3
Pin 10  (NRST) -> PD6
Pin 11    (0V) -> GND
Pin 12    (D0) -> PB0
Pin 14    (D1) -> PB1
Pin 16    (D2) -> PB2
Pin 18    (D3) -> PB3
Pin 20    (D4) -> PB4
Pin 22    (D5) -> PB5
Pin 24    (D6) -> PB6
Pin 26    (D7) -> PB7


A bunch more signals are available on the Electron, so I figure I may as well wire as many as I can to PD*. READY, /IRQ, and /NMI are obvious ones to do. Otherwise it's just address lines, which aren't that useful here, given that A14 and A15 are missing. I guess I'll pull in A0, seeing as it's also on the Tube connector.


If you do come up with a working open source PCB (say in KiCad). I would be happy to commission a batch of boards from China and distribute those in the UK for free or at cost. (https://pcbshopper.com/) :D
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Re: Open Source Logic Analyzer Experiments

Postby myelin » Thu Nov 23, 2017 8:48 pm

hoglet wrote:

Code: Select all

 Tube    lcsoft board        Cartridge
------   ------------    ----------------
Pin  2   (RnW) -> PD0 <- (RnW)   Pin A4 (Elk)/Pin A11 (Master)
                  PD2 <- (Rdy)   Pin A11 (Elk)/via wire/test Clip (Master)

Note that the cartridge pin for RnW differs between the Elk and Master.


Sounds good. I'll add in some jumpers so you can configure whether PD0 goes to A4/A11, and whether PD2 goes to A11 or not. I'll put headers so either can go to a test clip, which would make for less messing with hardware when switching machines if you felt like swapping the pin assignments when running decode6502 and wiring RDY into PD0 for a Master.
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Re: Open Source Logic Analyzer Experiments

Postby myelin » Thu Nov 23, 2017 10:54 pm

fordp wrote:If you do come up with a working open source PCB (say in KiCad). I would be happy to commission a batch of boards from China and distribute those in the UK for free or at cost. (https://pcbshopper.com/) :D


That would be excellent!

Not done yet, but here's the current design: https://github.com/google/myelin-acorn- ... ge_adapter
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Re: Open Source Logic Analyzer Experiments

Postby marcusjambler » Thu Nov 23, 2017 11:30 pm

Registering interest in a complete board please :D

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Re: Open Source Logic Analyzer Experiments

Postby fordp » Fri Nov 24, 2017 7:50 am

marcusjambler wrote:Registering interest in a complete board please :D


Obviously never seen my soldering ;)
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Re: Open Source Logic Analyzer Experiments

Postby marcusjambler » Fri Nov 24, 2017 9:10 am

Hahahaaa I'm being lazy of course.... a bare board will also be awesome :D

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Re: Open Source Logic Analyzer Experiments

Postby dominicbeesley » Fri Nov 24, 2017 10:24 am

Please put me down for one too!

before I order, is this the right board https://www.amazon.co.uk/EZ-USB-FX2LP-C ... B008B48VDA

D

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Re: Open Source Logic Analyzer Experiments

Postby hoglet » Fri Nov 24, 2017 11:09 am

dominicbeesley wrote:before I order, is this the right board https://www.amazon.co.uk/EZ-USB-FX2LP-C ... B008B48VDA

It may work, but you might have some additional fiddling to do. It is a different board to the one I have.

I would recommend buying the one from Hobby Components, as they have programmed the EEPROM with the correct USB ID:
http://hobbycomponents.com/cypress/674- ... c-analyser
This is guaranteed to work "out of the box" with sigrok.

Will you be using Linux or Windows?

Dave

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Re: Open Source Logic Analyzer Experiments

Postby dominicbeesley » Fri Nov 24, 2017 11:29 am

Thanks Dave,

I've ordered that.

I'll most probably be using Windows+Cygwin as that is what is physically easiest, though I could use Linux as I'm about to decommission my previous i7 desktop and might install Linux on there.

D

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Re: Open Source Logic Analyzer Experiments

Postby dp11 » Fri Nov 24, 2017 11:55 am

Could the cartridge adapter also have space for the level shifters and a pizero?

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Re: Open Source Logic Analyzer Experiments

Postby myelin » Fri Nov 24, 2017 6:57 pm

dp11 wrote:Could the cartridge adapter also have space for the level shifters and a pizero?


You want one of my Elk PiTubeDirect boards, which uses a CPLD for level shifting and to provide the /TUBE signal. Dave Hitchins has a few of them — ping him and he’ll post you one. They’re just bare boards but as long as you can solder the TQFP chip, you’ll be fine.

I’m considering putting a 74HCT00 and a 74HCT08 chip on the FX2 board, to generate /TUBE, which would let you use it as a Tube adapter, but at 5V, so you’d still need a separate level shifter board like one of the Sundby ones.
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Re: Open Source Logic Analyzer Experiments

Postby hoglet » Fri Nov 24, 2017 8:24 pm

I've been doing some quite extensive testing over the last few days, running the Dormann and Bruce Clark test suites. This is helped iron out a few bugs in the decoder.

This has involved some long captures of up to 60s of bus data (which seems to be the max the FX2 board can do), which results in a 1.44GB capture file containing 720 million samples. In doing this, it's becoming apparent that asynchronously sampling the data bus 100% reliably is actually quite tricky @ 12MHz sample rate.

To understand why, imagine a 6502 bus running at 2MHz, and being sampled at 12MHz. What you will typically see is samples like the following:

Code: Select all

Phi2 Data
   1 DD
   1 EE
   1 FF______
   0 AA
   0 BB
   0 CC
   1 DD
   1 EE
   1 FF______
   0 AA
   0 BB
   0 CC

Ideally, you want to sample the data bus exactly the falling edge of Phi2, which is what the 6502 itself does. So the question is, which data bus sample to take? FF or AA

It turns out that on the Beeb, using sample AA works more reliably, where as on the Elk and Master using FF works more reliably.

On the Beeb and Master, I've been able to tune things (in software) so the decoding seems to work perfectly. But on the Elk (which I've been testing today), neither works perfectly. About 0.0001% of the time the data bus is mis-sampled in a way that causes the decoder to flag an error.

It all boils down, I think, to 12MHz sampling (83.3ns) being just too imprecise.

The obvious solution is to increase the sampling rate. But that's not possible with the FX2 board, and the limitation is the USB bus bandwidth.

Also, I'm using a IC test clip on the 6502 directly, where as on the cartridge port the signal integrity will be worse, and the clock I believe is not actually Phi2, it's Phi0. (I haven't decided if this will make things better or worse!)

I'm wondering as myelin is going to the trouble of designing a PCB, whether it would be prudent to latch the data bus, using an octal transparent latch, like a 74LS373. This would give a much wider window for grabbing the correct data value, and probably eliminate the need to do system specific tweaking.

Dave

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Re: Open Source Logic Analyzer Experiments

Postby dp11 » Fri Nov 24, 2017 8:30 pm

Another option would be to change the fx2 to do synchronised sampling by feeding phi clock into the fx2. This also reduces the amount of captured data.

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Re: Open Source Logic Analyzer Experiments

Postby hoglet » Fri Nov 24, 2017 8:33 pm

dp11 wrote:Another option would be to change the fx2 to do synchronised sampling by feeding phi clock into the fx2. This also reduces the amount of captured data.

Yes, this would definitely help, assuming it can sample on the falling edge.

But I'm guessing we would have to write custom firmware for the FX2 to do this?

The sigrok fx2lwfa is open, so it would be possible:
https://github.com/sigrokproject/sigrok ... re-fx2lafw

I guess the changes might be needed here, to select the IFCLK as an external clock source.
https://github.com/sigrokproject/sigrok ... ion.c#L201

This would be very nice!

Dave

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Re: Open Source Logic Analyzer Experiments

Postby dp11 » Fri Nov 24, 2017 8:59 pm

I did lots of work with the fx2 years ago. So it should be possible. When I'm back in the UK I'll try and dig out some of my designs.

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Re: Open Source Logic Analyzer Experiments

Postby myelin » Sat Nov 25, 2017 7:59 am

If we’re not shooting for a wires-only design, the ideal would probably be to put a small CPLD (9536/72?) between the tube/cartridge interface and the FX2, and buffer *all* the signals at 2MHz, not just 16 of them.

If the FX2 can trigger off the falling PHI0/2 edge, maybe we can use its third input port for the same result, without any extra hardware, though. I don’t know much about that chip.
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Re: Open Source Logic Analyzer Experiments

Postby dp11 » Sat Nov 25, 2017 8:11 am

The fx2 can trigger on either edge of an external clock. It can capture up to 16bits on the clock edge.

10years ago I was streaming 24MSPS (8bit) constantly to the pc.

The newer fx3 can do 32bit sampling.

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Re: Open Source Logic Analyzer Experiments

Postby hoglet » Sat Nov 25, 2017 11:18 am

Dominic,
dp11 wrote:The fx2 can trigger on either edge of an external clock. It can capture up to 16bits on the clock edge.

Unfortunately, I don't think it's going to be possible to connect Phi2 directly to the FX2 external clock input (IFCLK), because the data sheet specifies a minimum clock speed of 5MHz, and that the clock should be continuous:
http://www.cypress.com/file/126446/download#page=125

This is probably why the current Sigrok FX2LAFW firmware doesn't support synchronous capture. It might be possible to make use of the 16MHz clock, but this is only present on the cartridge port, not the Tube. So I am thinking that latching the data bus with an octal latch or a small CPLD is the way to go.

This is all very frustrating, because this is so nearly working with a direct connection i.e. it works 99.999% of the time. It's only the Elk that seems to be problematic. I'll dig into this a bit more, because it may be mis-sampling due to noise on the clock.

From a timing perspective the 2MHZ 65C02A specifies a 50ns data setup time and a 10ns data hold time. So the window when the read data is guaranteed to be present on the data bus is only 60ns. Given that it's working at all with a 83ns sampling clock, in practice it can't be as bad as that. But I guess this indicates the timing margins in the Elk are tighter than in the Beeb/Master.


Dave

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Re: Open Source Logic Analyzer Experiments

Postby hoglet » Sat Nov 25, 2017 12:15 pm

Gosh, the FX2 technical manual (all 402 pages of it) is quite heavy going!
http://www.cypress.com/file/126446/download

Another option I think might be to use:
- Slave FIFO mode
- asynchronous
- connect Phi2 to SLWR (which seems to be Rdy1 pin) and use this a as write strobe
- invert the polarity of SLWR so it's active high (via the FIFOPINPOLAR register)

Data is then written to the FIFO each asserted-to-deasserted transition of SLWR, which would be the falling edge pf Phi2. The FX2 has a setup time of 9.6ns and a hold time of 0.0ns, which is much tighter than the 6502, so sampling should be reliable.

To do this I think the IFCONFIG register needs settings as follows:
- bit 7 = 1 (select the internal clock source for the interface clock)
- bit 6 = 1 (select 48MHz internal clock)
- bit 5 = 0 (disable IFCLK clock output)
- bit 4 = 0 (normal polarity for the interface clock)
- bit 3 = 1 (asynchronous mode, SLWR is used as a write strobe)
- bit 2 = 0 (disable GSTATE output
- bit 1,0 = 11 (slave FIFO mode)

But achieving this is probably a bigger change to the firmware, which currently runs in GPIF Master Mode.

Dave

Edit: fx2pipe looks very interesting:
http://www.triplespark.net/elec/periph/ ... 2pipe.html


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