Electron - Memory Detection Issues with the AP6

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daveejhitchins
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Electron - Memory Detection Issues with the AP6

Postby daveejhitchins » Sun Oct 01, 2017 6:32 am

This discussion arose during the BeebSCSI issue with production New AP5 thread. The first quote comes from this post.
Moved here as it's a separate issue. Mark

hoglet wrote:I think the root cause of this confusion is that when no serial port is present, a read of &FC65 returns &FC (i.e. the high byte of the address) due to data bus capacitance. This is sufficient to make the +1 ROM think there has been a a serial interrupt.
Dave . . . I have a similar, outstanding, issue associated with empty sideways bank detection (especially cartridge sockets!) with the AP6. Jonathan has had to add several NOPs, after writing to a sideways bank, before reading back. Sometimes this isn't enough (certain combinations of Elk/Plus 1). So, I was thinking . . . The common element is the Plus 1 - would it make sense to add a pull-up resistor to, probably, just one of the data lines in the Plus 1. If Jonathan can advise what data he uses for socket detection and then choose a line to pull-up that would fix both issues!

Dave H :D

p.s. I (or users) could carry out this mode when fitting the AP6. And I could add a description of the mod to the AP5 User Guide.
Parts: UM6502CE, GAL22V10D, GAL16V8D, AS6C62256A, TC514400AZ, WD1772, R6522, TMS27C512, AT28C256
Products: ARA II, ABR, ATI, AP6, MGC, AP5 . . .
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hoglet
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Re: BeebSCSI issue with production New AP5

Postby hoglet » Sun Oct 01, 2017 6:53 am

daveejhitchins wrote:The common element is the Plus 1 - would it make sense to add a pull-up resistor to, probably, just one of the data lines in the Plus 1.

My feeling is that's a bit drastic, and might possibly have unforeseen consequences (who knows what existing code might rely on the default behaviour). The MOS Tube detection code, for example. Also, the data bus is unbuffered, and pretty overloaded already.

The other common element is the Plus 1 Support ROM, and it seems both issues should be fixable in software. The RAM test could be made more robust by testing two locations with opposing values (e.g. 55 and AA).

There is plenty of free space in AP6v130.rom so we might as well use it!

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Re: Electron - Memory Detection Issues with the AP6

Postby daveejhitchins » Sun Oct 01, 2017 7:07 am

hoglet wrote:My feeling is that's a bit drastic, and might possibly have unforeseen consequences (who knows what existing code might rely on the default behaviour). The MOS Tube detection code, for example.
Not really . . . We know exactly what the Tube is looking for, so that wouldn't be an issue. However, for people with just the original Plus 1 support ROM or with the P.R.E.S. version - they would need to replace it and AP6 users would need an update!
hoglet wrote:The other common element is the Plus 1 Support ROM, and it seems both issues should be fixable in software. The RAM test could be made more robust by testing two locations with opposing values (e.g. 55 and AA).
Surely that would exhibit the same symptoms as you would still read the same value back after a write to a floating bus! Whereas a known pull-up would fix this!
hoglet wrote:There is plenty of free space in AP6v130.rom so we might as well use it!
I believe Jonathan used the serial code from the P.R.E.S. Plus 1 support IC and I know P.R.E.S. usd the code from the Acorn Plus 1 support - so the issue would affect all three ICs ?

Dave H :D
Parts: UM6502CE, GAL22V10D, GAL16V8D, AS6C62256A, TC514400AZ, WD1772, R6522, TMS27C512, AT28C256
Products: ARA II, ABR, ATI, AP6, MGC, AP5 . . .
For a price list, contact me at: Retro Hardware AT dave ej hitchins DOT plus DOT com

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hoglet
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Re: Electron - Memory Detection Issues with the AP6

Postby hoglet » Sun Oct 01, 2017 9:00 am

daveejhitchins wrote:
hoglet wrote:The other common element is the Plus 1 Support ROM, and it seems both issues should be fixable in software. The RAM test could be made more robust by testing two locations with opposing values (e.g. 55 and AA).
Surely that would exhibit the same symptoms as you would still read the same value back after a write to a floating bus! Whereas a known pull-up would fix this!

I would expect it would be more reliable, so long as the test seqence was
- write address A
- write address B
- read address A
- read address B

But I do think it's worth understanding what's actually going wrong with the current code:

Code: Select all

LDA &8008:EOR #&AA:STA &8008 :\ Modify version byte
NOP                        :\ Wait for floating bus to settle
CMP &8008:PHP                :\ EQ=RAM, NE=ROM/EEPROM/empty
EOR #&AA:STA &8008           :\ Restore byte
.RomTestLp
LDA &8008:EOR &8008:BEQ RomTestOk :\ Bytes match
\ If empty socket, Cx EOR Cx -> 0x  %00xxxxxx
\ If EEPROM      , Cx EOR 8x -> 4x  %x1xxxxxx
ASL A:BPL RomTestOk          :\ Empty socket, bit 6 not toggling
LDY #ASC"E":BNE RomTestLp    :\ Toggling, must be EEPROM/empty
.RomTestOk
PLP:BNE RomTestNotRam        :\ NE from earlier, ROM or EEPROM or empty
LDY #ASC"R"                  :\ EQ from earlier, must be RAM
.RomTestNotRam
PLA:TAX
.RomTestSelect
STX &F4
LDA #&0C:STA ROMSEL
STX ROMSEL:RTS               :\ 50 bytes
.RomTestEnd

I actually don't understand how this is failing.

Consider the sequence:
STA &8008
NOP
CMP &8008

The data bus would look like:

Code: Select all

8D  // STA &8008 (4 cycles)
08
80
XX
EA  // NOP (2 cycles)
CD
CD  // CMP &8008 (4 cycles)
08
80
YY

Question: do you actually understand why this is unreliable?

I don't see how data bus capacitance alone can persist the value from XX to YY, as the data bus takes several different values in between, and the data bus is not split with buffers in any way.

There must be something else going on here.

Also, I don't understand this bit:

Code: Select all

LDA &8008:EOR &8008:BEQ RomTestOk :\ Bytes match
\ If empty socket, Cx EOR Cx -> 0x  %00xxxxxx
\ If EEPROM      , Cx EOR 8x -> 4x  %x1xxxxxx

I think I have observed the problem, but only when the MBR is fitted. Does this issue only occur with the MBR, or have you seen it at other times?

Dave

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1024MAK
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Re: Electron - Memory Detection Issues with the AP6

Postby 1024MAK » Sun Oct 01, 2017 9:17 am

What actual values are being returned on the databus when there is no active device driving it?
Does the different hardware and connected expansions change this?

Could some of the strange behaviour be explained by the databus not actually floating, but being biased (maybe one line/bit, maybe more, maybe all eight) in the non-valid logic level area by the various devices and components connected to the bus. Then the bias being shifted by activity in the connected expansions maybe...

Mark
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hoglet
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Re: Electron - Memory Detection Issues with the AP6

Postby hoglet » Sun Oct 01, 2017 12:06 pm

Here's a test program for this false positive RAM detection:

Code: Select all

   10 CLS
   20 INPUT '"How many NOPs? " N
   30 P%=&2000
   40[OPT 0
   50 .test
   60 SEI
   70 LDX #&0F
   80 .loop
   90 LDA #&0C
  100 STA &FE05
  110 STX &FE05
  120 LDA &8008
  130 STA &2100,X
  140 EOR #&FF
  150 STA &8008
  160]
  170 IF N=0 GOTO 230
  180 FOR I=1 TO N
  190[OPT 0
  200 NOP
  210]
  220 NEXT
  230[OPT 0
  240 LDA &8008
  250 STA &2110,X
  260 DEX
  270 BPL loop
  280 LDA #&0C
  290 STA &FE05
  300 LDA &F4
  310 STA &FE05
  320 CLI
  330 RTS
  340]
  350 CALL test
  360 FOR A=0 TO 15
  370 PRINT ~A,~A?&2100,~A?&2110
  380 NEXT

This prints three columns of data:
- the ROM number
- the value initially read (which is then xor'd with &FF and written back)
- the value read back after a number of NOPs

Results with the MRB disabled:
IMG_1113.JPG

IMG_1114.JPG


Results with the MRB enabled:
IMG_1115.JPG

IMG_1116.JPG

IMG_1117.JPG

IMG_1118.JPG

IMG_1119.JPG


Looking at the results, the slots showing false positive RAM detection are 5, 6, 7 and F, all of which are on the AP6. (Slot 4 is real RAM on my system). You can clearly see the value is decaying back to &FF over time. It's also not specific to the MRB, it's just more pronounced because the CPU is running faster.

I've now understood how this is happening.

The AP6 contains a set of 74LS245A bus buffer that splits the data bus. This allows charge to be stored on the far side of these buffers on the AP6, even though several 6502 bus cycles have taken place in the mean time.

Dave, if you want to fix this with pull-ups, they would need to go on the AP6 itself. This is then not going to affect the values read back from unused devices in FCxx. So I don't think it's going to be possible to fix both issues with just one set of pull-ups.

I still think it's better to fix this in software, either by just amending the RAM detection to wait much longer, or by testing two separate locations.

Dave

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1024MAK
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Re: Electron - Memory Detection Issues with the AP6

Postby 1024MAK » Mon Oct 02, 2017 10:36 pm

Well done Dave =D>

Nice bit of detective work :D

Mark
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hoglet
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Re: Electron - Memory Detection Issues with the AP6

Postby hoglet » Tue Oct 03, 2017 6:31 am

Thanks for splitting the thread Mark.

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jgharston
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Re: Electron - Memory Detection Issues with the AP6

Postby jgharston » Tue Oct 03, 2017 7:50 pm

I've made some notes from both threads, I'll chuffle my machines around at the weekend to set up the Elk and do a bit of testing and code updates.

Code: Select all

$ bbcbasic
PDP11 BBC BASIC IV Version 0.25
(C) Copyright J.G.Harston 1989,2005-2015
>_


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