Electron ULA Schematics

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hoglet
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Electron ULA Schematics

Postby hoglet » Sun Oct 01, 2017 10:50 am

Hi all,

Edit: Here's Harry's second attempt at scanning these:
https://www.dropbox.com/s/xmr9h7srqpucj ... 7.pdf?dl=0


As mentioned in this thread, I've been back in contact with Harry Barman, one of the ex-Acorn engineers that worked on the Synertek version of the Electron ULA regarding the original schematics.

Harry still has copies of the original schematics for the Ferrantti version (designed I think by Steve Furber).

He's not had time to make high quality scans, but has given me permission to post these low quality scans.
elk-ula-scan_06-22-2015_11-41-48.pdf
(1.38 MiB) Downloaded 98 times

Many thanks to Harry for these.

In addition, he's also included an amusing saga that was written at the time:
elk-saga_06-22-2015_11-37-48.pdf
(454.17 KiB) Downloaded 103 times

Hopefully in the fullness of time we'll get a better quality versions, but these may well be good enough to answer some questions.

I'm just about to print them out...

Dave
Last edited by hoglet on Tue Oct 17, 2017 9:05 pm, edited 2 times in total.

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hicks
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Re: Electron ULA Schematics

Postby hicks » Sun Oct 01, 2017 11:20 am

That is awesome. Please pass on my thanks too if you have any further correspondence :)

I've been adding to the list of corner case questions I have about the cassette interface so hopefully this will really help. Higher quality scans would be useful, but considering I never expected to see any ULA schematics anything is better than nothing :lol: If he ever rescans, we'll have to organise a beer fund :)

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davidb
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Re: Electron ULA Schematics

Postby davidb » Sun Oct 01, 2017 11:49 am

That looks like a good start! Hopefully it will provide answers to those of you who are deeper into the function of the ULA than I have been. :)

The saga is quite the piece of social history, isn't it? ;)

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Re: Electron ULA Schematics

Postby hicks » Sun Oct 01, 2017 12:44 pm

Just printed this out and having a quick look through. Lots of faded spots including sheet headings. Can make out:-

  • Sheet 2 - (Video?) Address Generator
  • Sheet 3 - Cassette Output
  • Sheet 4 - ?? - Possibly cassette timing & sound related?
  • Sheet 5 - ??
  • Sheet 6 = (??) (Logic?) - Video related
  • Sheet 7 = ??
  • Sheet 8 = Ram Address Multiplexing
  • Sheet 9 = Master Timing & Control
  • Sheet 10 = Cassette (Input?)
  • Sheet 11 = Ram Data Interface
  • Sheet 12 = Processor Data Interface
  • Sheet (??) = (??) Interface

Last sheet might be sheet 1? Hopefully the ?? can be filled in after some time tracing through the circuits :)

Sheet 10 looks interesting to me for cassette input, I think it shows two latches after CASINX followed by a NOR gate which I assume is doing negative edge detection? I hope anyway, my knowledge of electronics is rather limited :)

edit: updated sheet names based on below post.
Last edited by hicks on Sun Oct 01, 2017 1:08 pm, edited 2 times in total.

paulb
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Re: Electron ULA Schematics

Postby paulb » Sun Oct 01, 2017 1:04 pm

Thanks to Harry for making these scans available!

Page 4/Sheet 5 might be related to the keyboard decoding, just from a quick look.
Page 5/Sheet 6 seems to have colour outputs, so it might be related to the palette.
Page 6/Sheet 7 might be related to the display logic, given some of the labels.
Page 7/Sheet 8 has "RAM address multiplexing" in the title.
Page 10/Sheet 11 has "RAM data interface" in the title.
Page 11/Sheet 12 has "processor data interface" in the title.

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1024MAK
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Re: Electron ULA Schematics

Postby 1024MAK » Sun Oct 01, 2017 3:44 pm

  • Sheet 2 - (Video?) Address Generator
  • Sheet 3 - Cassette Output
  • Sheet 4 - ?? - Possibly cassette timing & sound related?
  • Sheet 5 - ??
  • Sheet 6 = (??) (Logic?) - Video related
  • Sheet 7 = ??
  • Sheet 8 = Ram Address Multiplexing
  • Sheet 9 = Master Timing & Control
  • Sheet 10 = Cassette (Input?)
  • Sheet 11 = Ram Data Interface
  • Sheet 12 = Processor Data Interface
  • Sheet (??) = Processor Address Interface (maybe?)
  • Last page = Electron Expansion Bus Connector (list)

Mark
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BigEd
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Re: Electron ULA Schematics

Postby BigEd » Mon Oct 02, 2017 4:56 pm

hoglet wrote:He's not had time to make high quality scans, but has given me permission to post these low quality scans.

Excellent! Thanks Harry, and thanks Dave for pursuing the chase.

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Re: Electron ULA Schematics

Postby hicks » Sun Oct 15, 2017 10:35 am

1024MAK wrote:
  • Sheet (??) = Processor Address Interface (maybe?)

Mark


Not sure if that's the name written in the top left but it does appear to be what the sheet is doing. So sheet 13 "Processor Address Interface" it is.

In the bottom right there's "ICNTB" That is used on sheet 12 "Processor Data Interface" to clock 5 flipflops that appear to be the interrupt enabled register bits for display end, RTC, Rx Full, TX Empty and Hi Tone.

FWIW I had a quick look over the schematics last night and plan to have a more detailed look today as I want to try to answer some questions about when tx/rx/hitone interrupts can actually be generated. If it's of use to anyone, here's some rough orientation notes. Take everything with a pinch of salt as I'm making many assumptions and have yet to verify most of them.

Sheet 12 - Processor Data Interface

Bottom right is DIX0..DIX7 for data input bits.
DIX3..5 first go to three flipflops marked m0,m1,m2 possibly display mode register bits. clocked by I think it's "WLIB" ?
DIX2,3,4,5,6 also head up the page to a set of 5 flipflops which are latched using "ICNTB" and I believe are the interrupt enable registers.
The logic above those, I'm not sure about and haven't looked at.
Off to the left of those are a set of IRQ nor gates to build to master IRQ signal. Off to the left again of those are the interrupt source signals DISPENDB, RTCB etc It looks like those two plus HITONEB are latched whilst RD Full and TX Empty are not?
The mass of logic in the bottom left looks to be selection logic to pass data from the registers the CPU is reading data from to d0..d7, e.g selecting between memory read bits or interrupt state bits.

Sheet 10 - Cassette Input

Bottom right - RDRFB and RDRF is the read full interrupt logic.
Not fully worked out the logic here, but it looks like a 4bit counter clocked by the inverted output of a 2bit counter. Whatever the frame clock is, is being divided by four then used to count to 8. On 8, RD Full will be asserted and it looks like the STOP bit will be available in CDATA. RD Full is cleared anytime HITONE or CASSRD are asserted.

There's some reset logic for the two counters that I've not worked through yet.

To the left of all that is the "HITONEB" high tone interrupt signal. No idea where this is generated atm. It appears to feed into the logic that clocks the cas data register and generates RD Full interrupt and comes from "MONOINX" ?

Top right - Cas data shift register cd7..cd0. Top left not sure.

Bottom & Middle Left - Not sure yet, I'm guessing however it's related to working out how long an input pulse was high to determine if a 0 or 1 has been read in from the cassette, but that's just a guess.

So from this, it appears CASSRD or HIGHTONE asserted will clear "RD Full". Outside of that condition, anytime bit 3 is asserted i.e 8 bits have been clocked in, RD Full will be asserted.

Sheet 7 - Display Logic

Unrelated to the cassette logic I'm trying to trace, but this appears to be where the RTC and DISPEND interrupts are generated. Not sure what/how CKBAR works but there's a GMODE signal coming in from the bottom left. That is likely the "graphics mode", high in modes 0,1,2,4 and low in the two text modes 3 and 6. As that feeds into the dispend logic possibly to ensure it fires after line 250 or 256 depending on text vs gfx mode.

Sheet 4

Code: Select all


Bottom right: DIX[6] latched into "motor" register bit. The lack of CASMO on the input/output sheets does appear to confirm that interrupts can be generated regardless of motor status and for that matter in the case or RDRF possibly regardless of comm mode.

Top right: dix[1], dix[2] latched (by WCIB) into comm mode registers (MLAT4,5)

Bottom left: 8 bit general counter (C0) register loaded from databus by WC0B.
  On LDCNTX, bit CNT[8,9] are set and CNT[0..7] loaded based on inverted C0.

LDCNTX occurs based on CASRSTB in INPUT mode, or CNTB[9] in SOUND mode.

8 bit CNT0..7 ripple down count, clocked by FRQX. 2 more bits after that but CNT[8] appears to driven by CNT6 nor CNT7?

FRQX uses the comm mode to select between three input signals
  CK3      when comm mode = SOUND
  S8MB    when comm mode = OUTPUT
  CASSCK when comm mode = INPUT

Timing signals derived from CNT (clocked via FRQX above)
(NOTE: assumed / are broken traces and not included below, this might be
       wrong if those are just smudge marks :)
S0 - !(!LDCNTX + CNT0 + CNT2)
S1 - !(!LDCNTX + CNT2 + !CNT3 + !CNT4 + !CNT5)
S2 - !(!LDCNTX + CNT2 + CNT3 + !CNT4 + !CNT5 + !CNT6)
S5 - !(?? + !CNT3)
   - are the crossed out nor gates just "missing" or trace breaks too?
     if missing it looks like FRQX as well as !CNT1 merge without a gate?
S11 - !(!LDCNTX + CNT2 + !CNT3 + CNT4 + !CNT5 + CNT6)
S15 - !(!LDCNTX + CNT2 + !CNT3 + CNT4 + CNT5 + CNT6)


So what do these signals actually mean based on the counts? Not sure yet.


Anyhow, tons of vagueness remains. I might start redrawing some of this in kicad and learning some more about digital circuits is in order before I can understand more of this I think. It's tough to follow in places as the labelled are either hard to read or missing :( Crossing fingers for a higher res/clearer scan in the future :D

If I figure any of this out properly I'll edit this post and put in the final logic rather than wordy descriptions of each bit :)

Edit: Added some sheet 4 notes.
Last edited by hicks on Tue Oct 17, 2017 8:01 pm, edited 23 times in total.

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1024MAK
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Re: Electron ULA Schematics

Postby 1024MAK » Sun Oct 15, 2017 12:39 pm

If a high resolution grey scale scan could be done, then an image editing program may be able to improve the contrast of some of the hard to read detail.

Mark
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Re: Electron ULA Schematics

Postby hicks » Mon Oct 16, 2017 1:10 pm

I've mostly got a handle on the cassette input schematic now, however I'm still unsure of a few things, if anyone can shed light on these:-

  • MONOINX - where is this from?
  • MONOOUT - Where does this go?
  • S1...S15 - These look to be from Sheet 4 but I'm having a hard time working out just what they actually mean/do.
  • 2bit counter reset - There's CKxRST1 and CKxRST2 going into the bottom of the 2 bit counter, are these likely clear and set pins? to reset the counter to 0,0 or 1,1 depending?

I thought mono in/out might be the CAS In/Out pins on the ULA, but there's already CASINX elsewhere on the schematic that would make sense to be those pins?

I've cleaned up the original sheet 10 a little. There are a few additional labels on the original schematic but as I'm not sure what their naming convention is or what the labels meant, I've excluded them for now on this version.

https://www.dropbox.com/s/ewrt4of7qjbq7 ... .jpeg?dl=0

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1024MAK
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Re: Electron ULA Schematics

Postby 1024MAK » Mon Oct 16, 2017 1:53 pm

CKxRST1 and CKxRST2 may be some kind of clocked reset pulse, but guessing is not always reliable :mrgreen:

MONOINX, MONOOUT - I don't think it very likely that "audio" would be described as mono in a system that was never intended to have stereo sound. Therefore it's very likely that the signal names mean something very different.

Mark
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Re: Electron ULA Schematics

Postby hicks » Mon Oct 16, 2017 2:41 pm

It could mean mono tone, as in non varying, maybe for the constant hightone? It does look like MONOINX feeds straight back out as HIGHTONEB. So I was kind of assuming MONOINX is related to high tone detected, but then wonder where the circuit is that does that on the schematics as I don't see anything external to do it?

CAS RC was a candidate at first but it looks like it's connected to motor, gnd and +5v only? Unless they use it as an IO pin with the current cassette data bit 1/0 fed out to it and the time it takes to charge the cap enough for a 1 to be seen when you use it as an IN pin, to just happen to be the same time 10+ 1's would cover? That's pure speculation though, but I've yet to see any high tone counter based circuits? Could that kind of usage be possible? It seems a little too elaborate though vs just a several bit counter?

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Re: Electron ULA Schematics

Postby hicks » Mon Oct 16, 2017 8:20 pm

Looking more at sheet 4, I'm a little confused by whether the counter is an up or down counter. It looks like the ripple counter is wired ~Q to T which suggests a down counter? On sheet 10 the two and four bit counters are wired Q to T (up counter?)

However, when I look sheet 4 where it "loads" the CNT0 registers from the previous latched C0..c7 it does so via a nor gate and I think active low LDCNTX. Which if I'm not reading this wrong, means a C0..C7 value of three "11000000" would end up loaded into the CNT0 as "00111111" does it make sense that a load of 3 would count down from 252? Maybe it does from the point of view of the sound where 1MHz/(16*(S+1)) would mean loading a low value of S like 3, would need a large count down, where as loading a higher S=250 would need to reach 0 faster to produce the higher frequency. Sound fwiw appears to make use of 3 extra bits.

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Re: Electron ULA Schematics

Postby hicks » Tue Oct 17, 2017 6:30 pm

Interestingly it looks like the "div 13" pin doesn't seem to be present anywhere. I was under the impression the div13 was used in combination with the 16MHz clock to derive an ~1200Hz clock, but it looks like CNTB[8] from sheet 4 is being used for that (B being the suffix for "not").

Also, as far as S0,S1,S2,S5,S11,S15 go, I have no clue what they're representing. I'm assuming it's an "S" and not a "5" too. With the added issue that S15 appears to used along with an 8MHz clock to generate CASSCK but CASSCK appears to be what clocks the counter that S15 is derived from #-o

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hoglet
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Re: Electron ULA Schematics

Postby hoglet » Tue Oct 17, 2017 9:01 pm

I've just had a second email from Harry:
Hi - good to see the ULA schematics have excited some attention!

I had another go at scanning. Hopefully a bit better this time. I also found a sheet detailing some of the special I/Os. The scans are taken from 2nd generation A4 photocopies so there probably isn't much more detail to be gleaned from them.

Here's a copy of the updated file (too large to post!):
https://www.dropbox.com/s/xmr9h7srqpucj ... 7.pdf?dl=0

Dave

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Re: Electron ULA Schematics

Postby BigEd » Tue Oct 17, 2017 9:05 pm

Ah, so the MONO signals relate to the monostable using external RC components. We saw two off-sheet connectors because they go to the periphery of the chip - but only to one pin. Maybe.

(Nice one Dave!)

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Re: Electron ULA Schematics

Postby hicks » Tue Oct 17, 2017 9:36 pm

Dave thanks for uploading those, I'll take a look at them tomorrow and see if they fill in some of the blanks (literally h :lol: )

One thing I've noticed whilst looking at cassette output, sheet 3. There's a 4 bit counter that sets TX Empty to "1" when it has counted from 0 to 10. As long as TX Empty is "0", the clock (CNTB8) will drive the shift register. So it looks like 10 bits are shifted out after each write (the write resets the counter and in turn TX Empty to enable the clock to shift out again) which is what you'd expect with start bit, 8 data and stop bit. but...

This means TX Empty is not set after data bit 8 is pushed out but after the final stop bit? Unless I'm missing something? Only reason I'm kind of obsessing over the details on this, is that I think some games rely on TX interrupt for timing? Whether 2 bits of time difference would impact them I'm not sure, but it sounds like it might.

@BigEd: I'm not sure about it tbh. MONOOUT looks to be set based on whether two consecutive input bits are the same (CASCOMP) but then there's a batch of logic that uses S5, S2, S11 and S15 so I'm really not sure under what circumstances monoout is high/low. I'm speculating though on the fact I've not found anywhere that does a count for hightone yet and that MONOIN is used for hightone, that it is somehow getting set to 1 to charge the cap when there's consecutive 1's and 0 otherwise (there shouldn't ever be consecutive 0's I don't think?) which will discharge it. From that if the RC is setup such that it reaches the logic 1 level after a suitable time period for at least 10 bits > 8.33ms ? then that would count as hightone.

That is total speculation though, I'm really not sure at all how the MONOCNT, DATACNT and CDIN latches are operating as I do not understand the logic behind the S* signals.

Edit: This post mentions the RC timing to be 56ms. Which would suggest 60-70 consecutive 1's for hightone detection (well for cap full, logic 1 level might be reached earlier?). I recall another post on the forums that mentioned finding ~60 x1's were needed for reliable hightone? Not willing to say that's how it's working, but it does seem to fit?

Edit2: Having looked at page 1 of the new schematics, well I guess we know what monoin/out are doing now, they're the CAS RC in/out pin :)


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