Electron ULA Schematics

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hoglet
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Electron ULA Schematics

Postby hoglet » Sun Oct 01, 2017 10:50 am

Hi all,

Edit: Here's Harry's second attempt at scanning these:
https://www.dropbox.com/s/xmr9h7srqpucj ... 7.pdf?dl=0


As mentioned in this thread, I've been back in contact with Harry Barman, one of the ex-Acorn engineers that worked on the Synertek version of the Electron ULA regarding the original schematics.

Harry still has copies of the original schematics for the Ferrantti version (designed I think by Steve Furber).

He's not had time to make high quality scans, but has given me permission to post these low quality scans.
elk-ula-scan_06-22-2015_11-41-48.pdf
(1.38 MiB) Downloaded 120 times

Many thanks to Harry for these.

In addition, he's also included an amusing saga that was written at the time:
elk-saga_06-22-2015_11-37-48.pdf
(454.17 KiB) Downloaded 120 times

Hopefully in the fullness of time we'll get a better quality versions, but these may well be good enough to answer some questions.

I'm just about to print them out...

Dave
Last edited by hoglet on Tue Oct 17, 2017 9:05 pm, edited 2 times in total.

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Re: Electron ULA Schematics

Postby hicks » Sun Oct 01, 2017 11:20 am

That is awesome. Please pass on my thanks too if you have any further correspondence :)

I've been adding to the list of corner case questions I have about the cassette interface so hopefully this will really help. Higher quality scans would be useful, but considering I never expected to see any ULA schematics anything is better than nothing :lol: If he ever rescans, we'll have to organise a beer fund :)

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Re: Electron ULA Schematics

Postby davidb » Sun Oct 01, 2017 11:49 am

That looks like a good start! Hopefully it will provide answers to those of you who are deeper into the function of the ULA than I have been. :)

The saga is quite the piece of social history, isn't it? ;)

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Re: Electron ULA Schematics

Postby hicks » Sun Oct 01, 2017 12:44 pm

Just printed this out and having a quick look through. Lots of faded spots including sheet headings. Can make out:-

  • Sheet 2 - (Video?) Address Generator
  • Sheet 3 - Cassette Output
  • Sheet 4 - ?? - Possibly cassette timing & sound related?
  • Sheet 5 - ??
  • Sheet 6 = (??) (Logic?) - Video related
  • Sheet 7 = ??
  • Sheet 8 = Ram Address Multiplexing
  • Sheet 9 = Master Timing & Control
  • Sheet 10 = Cassette (Input?)
  • Sheet 11 = Ram Data Interface
  • Sheet 12 = Processor Data Interface
  • Sheet (??) = (??) Interface

Last sheet might be sheet 1? Hopefully the ?? can be filled in after some time tracing through the circuits :)

Sheet 10 looks interesting to me for cassette input, I think it shows two latches after CASINX followed by a NOR gate which I assume is doing negative edge detection? I hope anyway, my knowledge of electronics is rather limited :)

edit: updated sheet names based on below post.
Last edited by hicks on Sun Oct 01, 2017 1:08 pm, edited 2 times in total.

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Re: Electron ULA Schematics

Postby paulb » Sun Oct 01, 2017 1:04 pm

Thanks to Harry for making these scans available!

Page 4/Sheet 5 might be related to the keyboard decoding, just from a quick look.
Page 5/Sheet 6 seems to have colour outputs, so it might be related to the palette.
Page 6/Sheet 7 might be related to the display logic, given some of the labels.
Page 7/Sheet 8 has "RAM address multiplexing" in the title.
Page 10/Sheet 11 has "RAM data interface" in the title.
Page 11/Sheet 12 has "processor data interface" in the title.

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Re: Electron ULA Schematics

Postby 1024MAK » Sun Oct 01, 2017 3:44 pm

  • Sheet 2 - (Video?) Address Generator
  • Sheet 3 - Cassette Output
  • Sheet 4 - ?? - Possibly cassette timing & sound related?
  • Sheet 5 - ??
  • Sheet 6 = (??) (Logic?) - Video related
  • Sheet 7 = ??
  • Sheet 8 = Ram Address Multiplexing
  • Sheet 9 = Master Timing & Control
  • Sheet 10 = Cassette (Input?)
  • Sheet 11 = Ram Data Interface
  • Sheet 12 = Processor Data Interface
  • Sheet (??) = Processor Address Interface (maybe?)
  • Last page = Electron Expansion Bus Connector (list)

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Re: Electron ULA Schematics

Postby BigEd » Mon Oct 02, 2017 4:56 pm

hoglet wrote:He's not had time to make high quality scans, but has given me permission to post these low quality scans.

Excellent! Thanks Harry, and thanks Dave for pursuing the chase.

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Re: Electron ULA Schematics

Postby hicks » Sun Oct 15, 2017 10:35 am

1024MAK wrote:
  • Sheet (??) = Processor Address Interface (maybe?)

Mark


Not sure if that's the name written in the top left but it does appear to be what the sheet is doing. So sheet 13 "Processor Address Interface" it is.

In the bottom right there's "ICNTB" That is used on sheet 12 "Processor Data Interface" to clock 5 flipflops that appear to be the interrupt enabled register bits for display end, RTC, Rx Full, TX Empty and Hi Tone.

FWIW I had a quick look over the schematics last night and plan to have a more detailed look today as I want to try to answer some questions about when tx/rx/hitone interrupts can actually be generated. If it's of use to anyone, here's some rough orientation notes. Take everything with a pinch of salt as I'm making many assumptions and have yet to verify most of them.

Sheet 12 - Processor Data Interface

Bottom right is DIX0..DIX7 for data input bits.
DIX3..5 first go to three flipflops marked m0,m1,m2 possibly display mode register bits. clocked by I think it's "WLIB" ?
DIX2,3,4,5,6 also head up the page to a set of 5 flipflops which are latched using "ICNTB" and I believe are the interrupt enable registers.
The logic above those, I'm not sure about and haven't looked at.
Off to the left of those are a set of IRQ nor gates to build to master IRQ signal. Off to the left again of those are the interrupt source signals DISPENDB, RTCB etc It looks like those two plus HITONEB are latched whilst RD Full and TX Empty are not?
The mass of logic in the bottom left looks to be selection logic to pass data from the registers the CPU is reading data from to d0..d7, e.g selecting between memory read bits or interrupt state bits.

Sheet 10 - Cassette Input

Bottom right - RDRFB and RDRF is the read full interrupt logic.
Not fully worked out the logic here, but it looks like a 4bit counter clocked by the inverted output of a 2bit counter. Whatever the frame clock is, is being divided by four then used to count to 8. On 8, RD Full will be asserted and it looks like the STOP bit will be available in CDATA. RD Full is cleared anytime HITONE or CASSRD are asserted.

There's some reset logic for the two counters that I've not worked through yet.

To the left of all that is the "HITONEB" high tone interrupt signal. No idea where this is generated atm. It appears to feed into the logic that clocks the cas data register and generates RD Full interrupt and comes from "MONOINX" ?

Top right - Cas data shift register cd7..cd0. Top left not sure.

Bottom & Middle Left - Not sure yet, I'm guessing however it's related to working out how long an input pulse was high to determine if a 0 or 1 has been read in from the cassette, but that's just a guess.

So from this, it appears CASSRD or HIGHTONE asserted will clear "RD Full". Outside of that condition, anytime bit 3 is asserted i.e 8 bits have been clocked in, RD Full will be asserted.

Sheet 7 - Display Logic

Unrelated to the cassette logic I'm trying to trace, but this appears to be where the RTC and DISPEND interrupts are generated. Not sure what/how CKBAR works but there's a GMODE signal coming in from the bottom left. That is likely the "graphics mode", high in modes 0,1,2,4 and low in the two text modes 3 and 6. As that feeds into the dispend logic possibly to ensure it fires after line 250 or 256 depending on text vs gfx mode.

Sheet 4

Code: Select all


Bottom right: DIX[6] latched into "motor" register bit. The lack of CASMO on the input/output sheets does appear to confirm that interrupts can be generated regardless of motor status and for that matter in the case or RDRF possibly regardless of comm mode.

Top right: dix[1], dix[2] latched (by WCIB) into comm mode registers (MLAT4,5)

Bottom left: 8 bit general counter (PD) register loaded from databus by WC0B.
  On LDCNTX, bit CNT[8,9] are set and CNT[0..7] bits may or may not be reset.
 
Load looks to be done via a reset which only makes sense to me if the CNT bits are known to be all 1's at the time the RESET is done. Since a 0 in PD would cause a reset so CNT become 0 too. However a 1 in PD would not cause a reset, leaving CNT as whatever happened to be in the CNT?)

LDCNTX occurs based on CASRSTB in INPUT mode, or CNTB[9] in SOUND mode.

8 bit CNT0..7 ripple down count, clocked by FRQX. 2 more bits after that but CNT[8] appears to driven by CNT6 nor CNT7?

FRQX uses the comm mode to select between three input signals
  CK3      when comm mode = SOUND
  S8MB    when comm mode = OUTPUT
  CASSCK when comm mode = INPUT

Timing signals derived from CNT (clocked via FRQX above)
(NOTE: assumed / are broken traces and not included below, this might be
       wrong if those are just smudge marks :)
S0 - !(!LDCNTX + CNT0 + CNT2)
S1 - !(!LDCNTX + CNT2 + !CNT3 + !CNT4 + !CNT5)
S2 - !(!LDCNTX + CNT2 + CNT3 + !CNT4 + !CNT5 + !CNT6)
S5 - !(?? + !CNT3)
   - are the crossed out nor gates just "missing" or trace breaks too?
     if missing it looks like FRQX as well as !CNT1 merge without a gate?
S11 - !(!LDCNTX + CNT2 + !CNT3 + CNT4 + !CNT5 + CNT6)
S15 - !(!LDCNTX + CNT2 + !CNT3 + CNT4 + CNT5 + CNT6)


So what do these S* signals actually mean based on the counts? Anyone able to work that through?

If I figure any of this out properly I'll edit this post and put in the final logic rather than wordy descriptions of each bit :)

Edit: Added some sheet 4 notes.
Last edited by hicks on Wed Oct 18, 2017 12:34 pm, edited 26 times in total.

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Re: Electron ULA Schematics

Postby 1024MAK » Sun Oct 15, 2017 12:39 pm

If a high resolution grey scale scan could be done, then an image editing program may be able to improve the contrast of some of the hard to read detail.

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Re: Electron ULA Schematics

Postby hicks » Mon Oct 16, 2017 1:10 pm

I've mostly got a handle on the cassette input schematic now, however I'm still unsure of a few things, if anyone can shed light on these:-

  • MONOINX - where is this from?
  • MONOOUT - Where does this go?
  • S1...S15 - These look to be from Sheet 4 but I'm having a hard time working out just what they actually mean/do.
  • 2bit counter reset - There's CKxRST1 and CKxRST2 going into the bottom of the 2 bit counter, are these likely clear and set pins? to reset the counter to 0,0 or 1,1 depending?

I thought mono in/out might be the CAS In/Out pins on the ULA, but there's already CASINX elsewhere on the schematic that would make sense to be those pins?

I've cleaned up the original sheet 10 a little. There are a few additional labels on the original schematic but as I'm not sure what their naming convention is or what the labels meant, I've excluded them for now on this version.

https://www.dropbox.com/s/ewrt4of7qjbq7 ... .jpeg?dl=0

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Re: Electron ULA Schematics

Postby 1024MAK » Mon Oct 16, 2017 1:53 pm

CKxRST1 and CKxRST2 may be some kind of clocked reset pulse, but guessing is not always reliable :mrgreen:

MONOINX, MONOOUT - I don't think it very likely that "audio" would be described as mono in a system that was never intended to have stereo sound. Therefore it's very likely that the signal names mean something very different.

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Re: Electron ULA Schematics

Postby hicks » Mon Oct 16, 2017 2:41 pm

It could mean mono tone, as in non varying, maybe for the constant hightone? It does look like MONOINX feeds straight back out as HIGHTONEB. So I was kind of assuming MONOINX is related to high tone detected, but then wonder where the circuit is that does that on the schematics as I don't see anything external to do it?

CAS RC was a candidate at first but it looks like it's connected to motor, gnd and +5v only? Unless they use it as an IO pin with the current cassette data bit 1/0 fed out to it and the time it takes to charge the cap enough for a 1 to be seen when you use it as an IN pin, to just happen to be the same time 10+ 1's would cover? That's pure speculation though, but I've yet to see any high tone counter based circuits? Could that kind of usage be possible? It seems a little too elaborate though vs just a several bit counter?

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Re: Electron ULA Schematics

Postby hicks » Mon Oct 16, 2017 8:20 pm

Looking more at sheet 4, I'm a little confused by whether the counter is an up or down counter. It looks like the ripple counter is wired ~Q to T which suggests a down counter? On sheet 10 the two and four bit counters are wired Q to T (up counter?)

However, when I look sheet 4 where it "loads" the CNT0 registers from the previous latched C0..c7 it does so via a nor gate and I think active low LDCNTX

Edit: What it looks like is happening is A C0..C7 value of three "11000000" would end up loaded into the CNT0 as "XX000000" where X means the CNT bit didn't get reset so it might have a 0 or 1 there. Does that make sense? Would seem viable only if you knew the CNT register was all 1's at the time you load via reset?
Last edited by hicks on Wed Oct 18, 2017 12:25 pm, edited 1 time in total.

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Re: Electron ULA Schematics

Postby hicks » Tue Oct 17, 2017 6:30 pm

Interestingly it looks like the "div 13" pin doesn't seem to be present anywhere. I was under the impression the div13 was used in combination with the 16MHz clock to derive an ~1200Hz clock, but it looks like CNTB[8] from sheet 4 is being used for that (B being the suffix for "not").

Also, as far as S0,S1,S2,S5,S11,S15 go, I have no clue what they're representing. I'm assuming it's an "S" and not a "5" too. With the added issue that S15 appears to used along with an 8MHz clock to generate CASSCK but CASSCK appears to be what clocks the counter that S15 is derived from #-o

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Re: Electron ULA Schematics

Postby hoglet » Tue Oct 17, 2017 9:01 pm

I've just had a second email from Harry:
Hi - good to see the ULA schematics have excited some attention!

I had another go at scanning. Hopefully a bit better this time. I also found a sheet detailing some of the special I/Os. The scans are taken from 2nd generation A4 photocopies so there probably isn't much more detail to be gleaned from them.

Here's a copy of the updated file (too large to post!):
https://www.dropbox.com/s/xmr9h7srqpucj ... 7.pdf?dl=0

Dave

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Re: Electron ULA Schematics

Postby BigEd » Tue Oct 17, 2017 9:05 pm

Ah, so the MONO signals relate to the monostable using external RC components. We saw two off-sheet connectors because they go to the periphery of the chip - but only to one pin. Maybe.

(Nice one Dave!)

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Re: Electron ULA Schematics

Postby hicks » Tue Oct 17, 2017 9:36 pm

Dave thanks for uploading those, I'll take a look at them tomorrow and see if they fill in some of the blanks (literally h :lol: )

One thing I've noticed whilst looking at cassette output, sheet 3. There's a 4 bit counter that sets TX Empty to "1" when it has counted from 0 to 10. As long as TX Empty is "0", the clock (CNTB8) will drive the shift register. So it looks like 10 bits are shifted out after each write (the write resets the counter and in turn TX Empty to enable the clock to shift out again) which is what you'd expect with start bit, 8 data and stop bit. but...

This means TX Empty is not set after data bit 8 is pushed out but after the final stop bit? Unless I'm missing something? Only reason I'm kind of obsessing over the details on this, is that I think some games rely on TX interrupt for timing? Whether 2 bits of time difference would impact them I'm not sure, but it sounds like it might.

@BigEd: I'm not sure about it tbh. MONOOUT looks to be set based on whether two consecutive input bits are the same (CASCOMP) but then there's a batch of logic that uses S5, S2, S11 and S15 so I'm really not sure under what circumstances monoout is high/low. I'm speculating though on the fact I've not found anywhere that does a count for hightone yet and that MONOIN is used for hightone, that it is somehow getting set to 1 to charge the cap when there's consecutive 1's and 0 otherwise (I don't think there should ever be consecutive 0's?) which will discharge it. From that if the RC is setup such that it reaches the logic 1 level after a suitable time period for at least 10 bits > 8.33ms ? then that would count as hightone.

That is total speculation though, I'm really not sure at all how the MONOCNT, DATACNT and CDIN latches are operating as I do not understand the logic behind the S* signals.

Edit: This post mentions the RC timing to be 56ms. Which would suggest 60-70 consecutive 1's for hightone detection (well for cap full, logic 1 level might be reached earlier?). I recall another post on the forums that mentioned finding ~60 x1's were needed for reliable hightone? Not willing to say that's how it's working, but it does seem to fit?

Edit2: Having looked at page 1 of the new schematics, well I guess we know what monoin/out are doing now, they're the CAS RC in/out pin :)

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Re: Electron ULA Schematics

Postby hicks » Fri Oct 20, 2017 12:06 pm

Realised that whilst B is used to denote the inverted counterpart of a signal in numerous places on the schematics, on sheet 4, FRQ2 is not actually S8MB. It's using "S8M13" which is the "S16M13" signal divided by two. So it's actually a 615.38kHz signal. That will then (in comm output mode at least) toggle, CNT[8] at 2.4kHz which in turn will clock the output shift circuitry at the expected 1200Hz.

Deciphering some of the signal names is really tough :( Although at least that one is visible :)

I've worked through some of the S* signals for when they assert (usually seems to be for a 4 clock period too) but I'm not sure on S0 or S5 as both are derived from that set of NOR gates that are crossed out and some of the pathing doesn't make sense if you assume in their place is a straight through wire.

That said, it's a little clearer now why TX/RD interrupts can still fire at any time. Both are clocked from the multi counter always so with the exception of mode dependant reset criteria (during hightone, tx register write etc) they'll keep potentially generating interrupts. Since the multi counter can be one of three different frequencies, they won't always fire with the same timing in different modes (like sound).

There looks to be some interesting quirks too. For example sound and cassette output shifting triggers off CNT[8] (or CNT[9] for sound) but CNT[8] is setup to toggle not on CNT[7] but on both CNT[6] and CNT[7]. Loading looks odd too as it happens via the reset pin which can only load a "0".

I have a sneaky suspicion that the long periods of high tone might be related to helping the cassette input synchronise. As sheet 10 shows CASSCK depends on S15 which itself depends on CASSCK coupled with multi counter being reset after detecting an edge. Not sure how DATACNT comes into play on that one though.

Not sure how much more I'm going to try to work out on this. I feel I've got a good enough understanding conceptually (despite being iffy on many of the details) of how it works to ensure interrupts are triggering in suitable states in my core now and identified an issue with my RD Full logic which was working off negedge and not free running, plus the need to adjust multi counter to clock off of three different frequencies.

Anyhow, hopefully some of these notes will be of use to anyone who decides to have a crack at the schematics.

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Re: Electron ULA Schematics

Postby hicks » Sat Oct 21, 2017 2:30 pm

I believe I've almost understood how Sheet 4 and 10 works now and for the most part sheet 3.

So here's my final take on Sheet 10, cassette input.

Sheet 10

DATACNT I'm still not sure on. It enables or disables the ability for the edge detection/CASCOMP to reset the multi counter.

The multi counter restarts counting down each time an edge/reset occurs (note: due to the way "reset" of the counter works. You must load the counter register with all 0's. Only bits you loaded with a 0 will ever get reset. Failure cause an incorrect pulse 1/0 to be identified.)

1 or 0
As for whether it's a 0 or 1 detected, that's down to CDIN. When the counter reaches ~240 (s2) a one bit is assumed and CDIN goes high. If however the counter makes it down to 168 without an edge/reset, that suggests a 1200Hz pulse instead and CDIN goes low. The value will not be locked into CDATA until the counter resets due to an edge though.

Since the counter is resetting 2 or 4 times depending on 1200Hz or 2400Hz, there's no single value to trigger the data shift register off of and clock CDATA in at 1200Hz. Instead FRAMECK is used. This triggers off of S1 and S11 which are set such that during a 2400Hz (high or low) it will trigger once and during a 1200Hz (high or low) it will trigger twice. The end result is whether 2x2400Hz or 1x1200Hz occurs it will have triggered four times.

This results in the CKRST counter toggling four times every 1200Hz and bits are shifted once this 2bit counter resets.

Only other part is that a high-tone or reaching a count of 8 bits shifted will reset the CKRST counter and the main bitshift counter. Then (I think) the CDCKCNT latch holds the 4 bit counter in reset. In addition it holds the 2 bit counter in reset until a start bit is detected. The 2 bit counter then comes out of reset and will after two more FRAMECK reset the CDCKCNT latch which enables the 4 bit counter to start counting every 4 FRAMECK.

What is not clear on the schematic is why there's two reset lines for the CKXRST 2 bit counter. I _think_ one is a reset and one is a set so that when a start bit is detected the counter comes out of reset only one or two FRAMECK away from clocking. Which would ensure the 2nd half of a 1200Hz pulse is ignored as the first half was not counted due to being held in reset.

Mono

Not sure on monocnt as the S5 line looks messy to work out what may be crossed out or not. I expect this is ensuring the RC charges when consecutive ones occur though. Exactly how it does so, not sure.

If a hightone occurs, RX Full interrupt is cleared and it will place the 2 and 4 bit counters into reset and that will be latched by CDCKCNT holding them in reset until a start bit even if hightone goes low again. Same occurs on clocking in the 8th data bit. At this point RX FULL interrupt is set.

Remaining Questions

Not sure why there's a range of 4 values for the S* detection points, possibly just pulse stretching? Or what S5 is and tbh CNT[8] toggling I've assumed occurs now when the counter wraps from 0->255 but it's really not clear with all the NOR gates crossed out how they impact the wiring.

FWIW cassette output is simpler and runs off the multi counter without reset, so just clocked every 1200Hz for shifting. Bottom half is likely the pseudo sine wave generation @ 2400Hz vs 1200Hz frequency.

Take the above with a big disclaimer that mistakes may have been made and led to iffy interpretations and I would not discount someone else coming along and saying, erm that's not remotely how it works because of X.. :lol:

Thanks again to Dave for chasing up these schematics, they're proving to be quite interesting (and annoying at the same time) to see how the ULA really worked. Now begins the work of redoing my cassette i/o to better match this for interrupt triggering :D

Edit: I've implemented a reasonably close approximation now of the cassette input circuitry with the exception of the hightone detection where I used a counter due to lack of CAS RC. Other than forgetting to set the HIGHTONE interrupt bit :oops: which resulted in quite a few hours debugging, it all appears to work fine. Still no idea what value S5 should be, but as that's hightone related, I'm not too worried.

Edit2: After implementing write, I've noticed despite asserting "TX Empty" after the 10th bit, this actually ends up on the scope as occurring after the 8th data bit and before the stop bit. Which in hindsight makes sense as there are two "sync" bits which end up holding the start and stop bit. So the AUG is correct, that the TX Empty occurs after the 8th bit and before the stop bit is output. Shifting actually stops at this point too, but the stop bit will still be read (again and again and again as hightone if no new byte is loaded in)

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Re: Electron ULA Schematics

Postby davidb » Sat Oct 28, 2017 12:29 pm

It's fascinating to read these interpretations of the schematics. Thanks for sharing your thoughts with us, hicks! It's interesting that developers of FPGA cores are now revisiting work done by the emulator authors, only now with hardware rather than software. :)

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Re: Electron ULA Schematics

Postby hicks » Tue Oct 31, 2017 7:25 pm

After reading this post it's clear there's still a gap in my understanding of the cassette loading circuits. My implementation will return "A0" rather than "B0" when running straight after load, it only returns B0 after a soft-reset. :-k

Reason is, after loading in my version, the last bit that ends up in CDATA (sheet 10) is the stop bit or subsequent hightone. RD Full will be active and eventually reset (if not read/cleared before hightone starts). Either way, my version ends up in a state where the 4 bit counter is being held in reset and the 2 bit counter is also held in reset due to CDCKCNT latch. The reset remains until CDATA goes to 0 (next start bit) as that brings the NOR gate CKXRST1 to have a 1 and 0 inputs, bringing the 2 bit cnt out of reset which eventually brings the 4 bit counter out of reset by clearing the latch (and in turn causes the NOR gate to now have another 1 input, such that the value in CDATA no longer plays a part in causing a reset)

Somehow however, the real electron is not doing this and I'm at a loss to see how/why. The only way I can see for the RD Full to trigger again is if CDATA ends up with a 0 in it. Otherwise the counters remain held in reset. The only way I can see that could happen, is if there's still data coming in on CASINX that is a 0 at the time of an edge. Yet loading has stopped by this point and even if there was 0's coming in, that would just mean there'd be a few more 90's making appearances in place of some of the 80's, so that doesn't seem too likely either.

Anyone looked at sheet 10 much that's able to see if I've made a mistake in how the two counters interact with the latch? Also the 2 bit flip flops appear to have two reset pins. I've assumed one is a reset and one a set, but not certain. Two resets to 0 would make little sense and neither would the circuit as a whole in that case. I'm missing something here.

](*,)

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Re: Electron ULA Schematics

Postby hicks » Sat Dec 09, 2017 12:41 am

Spent a little time the last couple of evenings going over sheet 7, the Display Logic and simulating the circuit. I feel I've got a reasonable handle on what all the parts are doing now (any propagation delays not withstanding) but there does appear to be an issue with the schematic (or my interpretation of it :cry: )

Bottom right just above VReset there's a gate labelled ENDCOUNT. This appears to trigger when the 10 bit counter = 625 (312.5 lines due to 31.25kHz clock) and async resets the counter back to 0. It also causes a short half a line out signal that's not readable but I'm assuming is related to ADDINTBAR (used on sheet 2) but yet to verify.

VReset appears to be triggered on a count of 628 which will never be reached (due to the reset on 625) and this would be used to reset the 2bit VSync counter to the right of it. There's been a few corrections made to the schematic around this bit of logic, maybe further changes were made? As it stands atm it looks like VSync wouldn't be generated due to lack of a reset which obviously isn't the case.

Is the schematic incorrect? Have I misread part of it?

I plan to do some more simulation over the weekend to see if I can infer from the Electron's PAL signal and the schematics what count VReset may actually be triggering on, assuming the schematic is wrong rather than me :)

Despite this issue though, sheet 7 is no longer complete gibberish to me. Another sheet nearly down :D

Edit: Resolved this. VReset is connecting to Q on CNT[12] causing it to trigger on a count of 564 rather than 628. That makes a lot more sense as 564 followed by 2.5 lines vsync (5 counts) and 28 lines inactive (56 counts) = 625 lines. Meaning V count of 0 is the first active line and that now ties in well with RTC interrupt occuring on line 100 (200 count). :)


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