New 65C02/W65C816 copro

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1024MAK
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Re: New 65C02/W65C816 copro

Postby 1024MAK » Sun Aug 13, 2017 11:22 am

The limitation of the Tube is simply that you are using the Beeb's original 2 MHz CPU to write or read to/from the Tube registers using normal memory write/read instructions. If you recreate the Tube ULA using modern silicon, you can increase the size of some of the Tubes FIFO memory buffers to a greater depth, which may help a bit (as long as the software on both sides is written to make use of this).

The other way, as you say is DMA. But how do you propose to stop the Beeb's CPU and take control of it's busses?

On the subject of a second processor system using a 6502 with more than 64 k bytes of RAM, the actual bank switching scheme makes a big difference in how useful it is. At least 16 kbytes needs to be the same memory (from the CPU's point of view) regardless of which banks are selected, so that area can be used for the control code. That does not mean that area cannot be switched in and out. The memory should be switched in reasonable sized chunks, but no bigger than 16 k bytes.

If the chucks are each 16 k bytes in size, then a three bit binary number can select any bank out of a 128k SRAM chip. That gives the programmer two 16k areas in the CPU memory map where they can map any chunk of the available 128 k of the SRAM chip. Plus a choice between two predetermined chunks for the remaining two 16k areas.

Or you can use a more complex scheme.

And which address(es) to use for the bank switching register(s)???

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Re: New 65C02/W65C816 copro

Postby BigEd » Sun Aug 13, 2017 11:33 am

(If anyone is building a new copro with bank switching, it would be great if they could follow the same scheme as used now in the Matchbox and the Pi-based copro, so that software can be portable across different implementations.)

See here and here:
Banked RAM in the 6502 models

There is 1MByte of external RAM available, if the Matchbox board is fully populated. That's half the physical memory, for technical reasons. The 6502 memory map is spilt into 8K pages using a set of eight (write-only) paging registers at &FEE0-&FEE7:

  • the register at &FEE0 controls the mapping of 0x0000-0x1FFF
  • the register at &FEE1 controls the mapping of 0x2000-0x3FFF, etc
  • page values of 0x00-0x07 are directed to fast internal block RAM (and this is the default).
  • page values of 0x80-0xFF are directed to slower external static RAM.
Note that the I/O space in 6502 page &FE is always present. All other RAM space is paged, including page &FF with the vectors, page zero and the stack page, and including the OS in the top 4k. Page these out only with suitable preparation.

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Re: New 65C02/W65C816 copro

Postby hoglet » Sun Aug 13, 2017 11:40 am

The 6502 Co Pro in the Matchbox Co Pro and in PiTubeDirect both implement banked memory using the following model:

The page size is 8KB, and so there are 8 bank selection registers:
- 0xFEE0 controls the memory mapped in to 0x0000-0x1FFF
- 0xFEE1 controls the memory mapped in to 0x2000-0x3FFF
- ...
- 0xFEE7 controls the memory mapped in to 0xE000-0xFFFF

Each of these registers is 8 bits wide, allowing up to 2MB of banked memory to be addressed.

So far only one application has been written that makes use of this: 6502 Life (github / forum thread)
Image

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Re: New 65C02/W65C816 copro

Postby cmorley » Mon Aug 14, 2017 10:15 am

OK, good info thanks all.

I put the footprint for the 16MB and 128KB memory parts on my dev board so I can test out both. I also made my dev board compatible with the 816 and 02 with a couple of jumpers and resisitors. Electrically there are a few pins which change meaning and more irriatingly direction.

A large chunk of the HDL will be the same with either processor. Maybe I'll end up with two variants... a 65C02 Acorn 2nd processor facsimilie and an '816 model.

1024mak wrote:The other way, as you say is DMA. But how do you propose to stop the Beeb's CPU and take control of it's busses?


I will have both so Tube ULA+. DMA the other way round so the host has direct access to the parasite memory.

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Re: New 65C02/W65C816 copro

Postby dominicbeesley » Mon Aug 14, 2017 2:48 pm

I wasn't (just) being facetious earlier. Once the graphics is moved off the beeb you'd have to rewrite all the MOS stuff that does screen stuff. The disk I/O on the beeb is pretty slow and making a 1MHz bus (or similar) for your 65816 board would be easier than the TUBE stuff.

It's where I ended up with my 6809 project, I'd already done the 65816 tube thing and decided what I'd rather have is something like a beeb but faster/better - rather than a beeb with something faster hanging off it hamstrung by the slow IO and 8 colour graphics. Porting the MOS and BASIC across to the 6809 has been a fairly slow process but porting to the 65816 should be a lot easier! (If I'd got a ReNula I'd probably have gone the other way)

I'll be interested to see where you go with this, I was initially excited by the 65816 but got frustrated as it never quite met my initial expectations. The 6309/6809 while slower have a nicer programming model. The bank switching in the '816 is a pretty blunt instrument a simple MMU (like the matchbox or as I'm going to do on my Mk.2 6809 like the CoCo3) should give a far nicer programming model.

D

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Re: New 65C02/W65C816 copro

Postby cmorley » Mon Aug 14, 2017 4:16 pm

Going a little OT: I have on my dev list to do a reversion of a 4meg type board... a '816 and 16MB on this would seem like a worthwhile prospect - especially if clocked at 20+MHz. That's a little way off for now.

A better programming model than the '816 would be to do an ARM 2nd processor... a 500MHz cortex A5 processor is cheaper than the 65C816 & SDRAM/DDR/DDR2 is cheap.

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Re: New 65C02/W65C816 copro

Postby pstnotpd » Mon Aug 14, 2017 6:39 pm

Acorn thought of the Beeb as a "platform" to try processor architectures using the tube/copro paradigm. I.e. the Beeb is an I/O processor while the copro does the processing heavy lifting. I remember Sophie Wilson talking about that in one of her rare interviews.

I just imagine leveraging the 65x line as I/O like that. How far could it have gone? Given that the AppleIIGS seems to have been limited not to compete with the MacIntosh and the 65802 was designed as a hardware replacement for the 6502

From what I've read the communicator seems a step back from this concept as it limits I/O by using the Electron ULA.

65816 based Beeb, music 5000 and/or SID, 4096 colors VGA/HDMI, Tube, backwards compatible....


..... I know, software can do that but it's a nice project :)

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Re: New 65C02/W65C816 copro

Postby cmorley » Mon Aug 21, 2017 1:05 pm

I ordered a 65C816 which arrived today... FedEx grumble grumble... so have one in stock now. I'm progressing the 65C02 2nd processor version & 128K SRAM first with my dev board. Still plenty of work to do on that but I am making progress.

I'll think about an '816 version after depending on demand. I designed the dev board to take an '02 or '816 & SRAM and/or DRAM so it's mainly a matter of sinking time into it...

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Re: New 65C02/W65C816 copro

Postby cmorley » Sun Aug 27, 2017 1:11 pm

So far so good...

For all you who like WIP project pics:

Photo1053.jpg


Photo1052.jpg


The RAM is on the underside.

I've already got the 2nd CPU running. Next step is the Tube ULA HDL.

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Re: New 65C02/W65C816 copro

Postby 1024MAK » Mon Aug 28, 2017 10:27 am

What, no blinking LEDs :shock:

Looks like good progress so far 8)

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Re: New 65C02/W65C816 copro

Postby cmorley » Mon Aug 28, 2017 11:15 am

1024MAK wrote:What, no blinking LEDs :shock:


Near the yellow link wire is a yellow 3mm LED :D

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Re: New 65C02/W65C816 copro

Postby dominicbeesley » Tue Aug 29, 2017 11:48 am

ooh! looks good

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Re: New 65C02/W65C816 copro

Postby cmorley » Wed Aug 30, 2017 3:40 pm

Despite the bird's nest of wires I've got raw flawless comms between host & parasite now. The signal integrity from my patch wires (coloured ribbon cable) is pretty poor with a lot of crosstalk but hey, if it works like that it should work with a propper cable. I need to add some snubber resistors, the edges from the modern logic driving the data bus are too sharp.

With the 1.10 client and 1.10 host (DFS 1.2) it now prints the banner on break... below the DFS & BASIC lines :? and the keyboard doesn't work. (The host speaker whistles a lot when you press a key so it is obviously locked in a spin-wait). I get a prompt but I'm not sure if it copied BASIC across yet or not. That's with the parasite IRQ & NMI implemented.

Do I need the host IRQ working (Q flag & reg 4) to get BASIC?

Something's not right so I'll keep following JGH's host source & client source through to see where it gets stuck...

Edit: I think it isn't executing from RAM properly... time to write some test code to test the RAM.

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Re: New 65C02/W65C816 copro

Postby cmorley » Wed Aug 30, 2017 8:59 pm

Humm... so I changed my IO address mask to copy the hardware and it works. I looked in the ROM and it appears that FEE0-FEF8 are unused (just &FF) but annexing this for IO seemed to have it over... presumably some comms subroutines use this memory. I'll search now I know what memory caused the problem.

So all my head scratching over my Tube ULA HDL and that was OK it seems.

Only got the 'weird' reg 3 one byte/two byte data available & full flags to sort out now (as per app note 4).

I vaguely recall seeing some speed test results maybe for the pitube or matchbox... is there a 'normal' benchmark?

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Re: New 65C02/W65C816 copro

Postby cmorley » Wed Aug 30, 2017 9:15 pm

hoglet wrote:The 6502 Co Pro in the Matchbox Co Pro and in PiTubeDirect both implement banked memory using the following model:

The page size is 8KB, and so there are 8 bank selection registers:
- 0xFEE0 controls the memory mapped in to 0x0000-0x1FFF
- 0xFEE1 controls the memory mapped in to 0x2000-0x3FFF
- ...
- 0xFEE7 controls the memory mapped in to 0xE000-0xFFFF


Humm... so I annexed that IO space and it wouldn't boot. I will have to look more deeply at what is going on. I extracted the client ROM from your VHD file and it differs only with 0s in FEF0-FEFF & the NMI vector points to FE00 instead of FEB3.

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Re: New 65C02/W65C816 copro

Postby hoglet » Wed Aug 30, 2017 9:22 pm

cmorley wrote:Humm... so I changed my IO address mask to copy the hardware and it works. I looked in the ROM and it appears that FEE0-FEF8 are unused (just &FF) but annexing this for IO seemed to have it over... presumably some comms subroutines use this memory. I'll search now I know what memory caused the problem.

I'm pretty sure FEE0-FEF7 is unused by the normal 6502 Tube ROM, as that's where we have placed the paging registers.

So do you have language transfer working now?
cmorley wrote:I vaguely recall seeing some speed test results maybe for the pitube or matchbox... is there a 'normal' benchmark?

You want to run CLOCKSP:
http://mdfs.net/Software/BBCBasic/Testing/

Use CLOCKSP if you are running Basic II (i.e. a Model B), and CLOCKSP4 if you are running Basic IV (i.e. a Master.

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Re: New 65C02/W65C816 copro

Postby cmorley » Wed Aug 30, 2017 9:45 pm

Yes normal BASIC 2 seems to transfer over OK now and runs it seems.

I will look into the IO address space decoding. I probably get aliased copies of the tube registers so the ROM->RAM copy was probably sending FFs to the host by mistake in all 4 fifos.... I bet that's what it is.

Thanks for the benchmark link.

There is still a lot of development to do - no paging yet for example.

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Re: New 65C02/W65C816 copro

Postby hoglet » Thu Aug 31, 2017 6:44 am

cmorley wrote:I will look into the IO address space decoding. I probably get aliased copies of the tube registers so the ROM->RAM copy was probably sending FFs to the host by mistake in all 4 fifos.... I bet that's what it is.

Yes, that would probably mess things up.

The copy runs up to FEEF, so only FEF0-FEFF is excluded.

I wonder if this is changing out bank switch registers?? Or whether I changed this limit....

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Re: New 65C02/W65C816 copro

Postby cmorley » Fri Sep 01, 2017 7:22 am

I assume your bank select gets triggered on the read during the ROM initialisation copy so the ROM copies the register value and writes the register - instead of copying the ROM value and writing to RAM on an original 2nd processor.

Still a long way to go but...

Photo1055.jpg


Not sure yet how fast the WDC CPU will go. That's somewhat going to depend on memory timings...

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Re: New 65C02/W65C816 copro

Postby hoglet » Fri Sep 01, 2017 9:25 am

cmorley wrote:I assume your bank select gets triggered on the read during the ROM initialisation copy so the ROM copies the register value and writes the register - instead of copying the ROM value and writing to RAM on an original 2nd processor.

Actually, it looks like I did a one byte patch to the Tube Client ROM to end the copy at &FEDF instead of &FEEF:
https://github.com/hoglet67/PiTubeDirec ... caf0c1a728
cmorley wrote:Still a long way to go but...

Photo1055.jpg

Not sure yet how fast the WDC CPU will go. That's somewhat going to depend on memory timings...

Can you load and save programmes?

Tube Elite is a pretty good stress test :D

Dave

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Re: New 65C02/W65C816 copro

Postby cmorley » Fri Sep 01, 2017 10:27 am

hoglet wrote:Actually, it looks like I did a one byte patch to the Tube Client ROM to end the copy at &FEDF instead of &FEEF:
https://github.com/hoglet67/PiTubeDirec ... caf0c1a728


Ah, in the pi you did. I was looking at the ROM I extracted from your VHDL for the fpga copro... that I don't think has that patch IIRC.

Can you load and save programmes?

Tube Elite is a pretty good stress test :D


Yes, I have a serial connection to my dev PC and can also omniflop a 5.25" disc image. I haven't implemented the reg3 flags properly yet (avail/full only simulate 1 byte but NMI is correct) so if it uses reg3 and relies on the flags it won't work. I will give it a go!

I also haven't done the host IRQ... does anything use this? From the Acorn 2nd Processor service manual it suggests that the link is not fitted from the factory.

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Re: New 65C02/W65C816 copro

Postby hoglet » Fri Sep 01, 2017 11:26 am

cmorley wrote:I also haven't done the host IRQ... does anything use this? From the Acorn 2nd Processor service manual it suggests that the link is not fitted from the factory.

No, nothing uses that at all.

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Re: New 65C02/W65C816 copro

Postby cmorley » Fri Sep 01, 2017 4:47 pm

Up and running.

Photo1058.jpg


The version I got from Ian Bell's website seems to be hacked with commander firebud instead of Jameson. You start with billions of credits and all the gear. Maybe I can find a different version. Is there any way to skip the intro? I tried the normal BBC version and never realised how slow it was!

I fixed the final hardware problem (I know about) on this dev board. I made a better header adapter for robustness and because the bird's nest was a signal integrity nightmare. I added series resistors to the datalines to limit the current from the modern logic buffer chip.

So it seems to run anywhere from 3MHz to 20MHz OK so far. Still haven't done the reg 3 flags so Elite doesn't use them.

Edit: I found the STH version of Tube Elite rather than the "executive" version. That seems to run fine too.

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Re: New 65C02/W65C816 copro

Postby cmorley » Tue Sep 05, 2017 3:18 pm

Ok, I'm not sure where I should go with this project anymore. Straw poll time.

I need some management features so was going to add those to the boot ROM or shoehorn them in somehow. Basic stuff like change the PLL divisors so I can change the clock speed on the fly. I am also tempted to add some extra hardware acceleration features maybe for sprites so the host processor only need copy instead of mask+write in sprite routines...

I've a lot of FPGA fabric left so I looked at how much I'd need for a 6502 core for management etc... and that isn't a lot. The problem I have now is that a soft core would be 2-5x faster than the physical WDC65C02 (which is an expensive chip)! I could release a cheaper _faster_ version without a physical CPU - but my point was to make a 2nd processor where you could point at the CPU, RAM and ULA instead of 1 monolithic IC!

Now the matchbox FPGA already exists and is great value so morphing towards that seems like a mistake...

So... I could:
A) Make with a CPU (accepting 6502 or '816) cost would be ~£50 I think - with hard and soft core mode.
B) Sell same with unpopulated CPU without CPU cost would be ~£35 I think
C) Just an FPGA + level shift & snubbers

The 65C02 variant would have 128KB (or maybe 256KB of SRAM). With the option to populate 16MB of SDRAM - only much use for the '816.

They'd be assembled, tested and ready to run. But I would make some bare PCBs available for hobby builders (maybe £5-£10? not sure yet)

So is there any appetite for me to make any of these options?

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Re: New 65C02/W65C816 copro

Postby 1024MAK » Wed Sep 06, 2017 7:09 am

Um, what's the price of the WDC65C02 CPUs that you are looking at?
I bought some about 3 or 4 years ago and although I forget how much I paid now, I don't remember the price being in the expensive range. I do remember that I bought them from a USA based supplier that has a UK area of their website so that you can buy in GBP.

I already have the Matchbox second processor, so not really looking in that direction. I also have a real Acorn second processor.
I think what I would be looking for would be a modern and simple 6502 second processor. Or the same, but with a W65C816.

It's been said so many times, but although lots of extra RAM would be nice, what software is likely going to be written that will make use of it? So 128k bytes, yes.256k bytes or 512k bytes maybe. But I'm not sure any more would be useful.

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Re: New 65C02/W65C816 copro

Postby cmorley » Wed Sep 06, 2017 8:06 am

1024MAK wrote:I do remember that I bought them from a USA based supplier that has a UK area of their website so that you can buy in GBP.


Mouser sell them. They are £6.29@1 or £5.29@10 + VAT. So £6.50 for the chip in tens plus an extra £1 or so for some 3.3v-5v buffers. That's pretty much a third of the bill of materials for one chip.

I already have the Matchbox second processor, so not really looking in that direction. I also have a real Acorn second processor.
I think what I would be looking for would be a modern and simple 6502 second processor. Or the same, but with a W65C816.

It's been said so many times, but although lots of extra RAM would be nice, what software is likely going to be written that will make use of it? So 128k bytes, yes.256k bytes or 512k bytes maybe. But I'm not sure any more would be useful.


Thanks, that validates my original intention. People who want Matchbox or Pis will already have them or be on their purchase list already. I agree about the memory size. Pin compatibility between '02 & '816 is pretty close - a couple of jumpers & pull ups are needed + support in the gate array for the 3rd address byte.

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Re: New 65C02/W65C816 copro

Postby DutchAcorn » Wed Sep 06, 2017 9:43 am

cmorley wrote:Mouser sell them. They are £6.29@1 or £5.29@10 + VAT. So £6.50 for the chip in tens plus an extra £1 or so for some 3.3v-5v buffers. That's pretty much a third of the bill of materials for one chip.

Chinese alternative?
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Re: New 65C02/W65C816 copro

Postby cmorley » Wed Sep 06, 2017 10:20 am

DutchAcorn wrote:Chinese alternative?


The problem with chips from eBay or aliexpress is you can end up with almost anything badged up as the part you wanted. Often old recycled parts labelled as newer faster parts. This happens a lot with eproms for example. I've had ancient TI EPROMs rebadged as 'genuine' ST parts - you only have to look at the die to see they are old TI let alone read the mfgs ident code. Processors could be old 4MHz or 10Mhz parts rebadged... not even WDC ones.

Sometimes you can get great recycled parts, sometimes good new parts and other times a package full of WEEE.

So reliability of parts & consistency of supply is a problem. That's why I only buy parts for the things I sell from main distributors (mouser/digikey).

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Re: New 65C02/W65C816 copro

Postby dominicbeesley » Wed Sep 06, 2017 10:32 am

I've had fakes (capacitors, ICs) from the big distributors, they get duped too! I even scrapped my old car when I got bored of replacing the HEI module only to find out that the parts distributor had been duped and were selling crap modules.

I have however, recently bought a number of chips from AliExpress direct from Schengen and not had a bad one yet....Ebay+Hong Kong seems to be a bit more hit and miss, I got a few i2s sound chips that the fake paint rubbed off to reveal the older/better chip that I actually wanted.

Back to the spec, I'd be interested in this only if it was a "real" processor. The PI/Matchbox/DE0+tube silencer pretty much have the soft-core field covered. Memory isn't much of an issue (anything over 128K would be enough, SRAM is probably easier?)

What I would like is a socketed ROM so I could write my own boot code and have non-host ROMS (I did this on my 65816 so I could free up a ROM slot on the beeb).

My main request would be to have a header (not necessarily fitted) that brought out all the main signals A[23..0], D[7..0], RnW..etc plus a few extras into/out of the FPGA for experimentation?

Price point is always a killer but I'd be prepared to pay more for something that a) had headers, b) used through hole ICs, c) used real processors. I'm not sure how far others would go in opening their wallets though...

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Re: New 65C02/W65C816 copro

Postby cmorley » Wed Sep 06, 2017 1:24 pm

dominicbeesley wrote:What I would like is a socketed ROM so I could write my own boot code and have non-host ROMS (I did this on my 65816 so I could free up a ROM slot on the beeb).

My main request would be to have a header (not necessarily fitted) that brought out all the main signals A[23..0], D[7..0], RnW..etc plus a few extras into/out of the FPGA for experimentation?

Price point is always a killer but I'd be prepared to pay more for something that a) had headers, b) used through hole ICs, c) used real processors. I'm not sure how far others would go in opening their wallets though...


I am using the user FLASH in the FPGA for the boot ROM. If I made this programmable in system would that be OK? There is 32KB+ UFM IIRC but I am only using 4 at the moment. (I kept all the FFs for the first 2KB of the Acorn boot ROM!)

I could put an unpopulated header on... so the 65xx signals and some spare 3.3v GPIO to a header? That wouldn't add significantly to the PCB cost. You could hook a ROM on to that. There will be the JTAG heade too (probably unpopulated because I'll likely use pogo pins to program it)

All except the processor would be surface mount because that is what is readily available nowadays....


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