Simple Electron flash cartridge with 39SF010 + 74HCT00

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myelin
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Simple Electron flash cartridge with 39SF010 + 74HCT00

Postby myelin » Wed Mar 15, 2017 5:38 pm

As I wait for my Plus 1 to make its way across the Atlantic to San Francisco, I'm making hardware project plans :)

I have a Scarab miniSpartan6+ FPGA board (Spartan 6 LX25) on the way, but wanted to start out with something a bit simpler. An SST39SF010 128kx8 flash chip plus a 74HCT00 quad NAND gate to convert phi1/RnW/nOE into nWR, nOE, and nCE, should make for a very cheap (US$3.50 including PCB) and convenient two-bank/32kB flash cartridge for the Electron. I have a bunch of prototype boards sitting around, including an STM32F4 DISCOVERY, with which I should be able to make a cartridge programmer/interface. I'll post more details in this thread!
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paulb
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Re: Simple Electron flash cartridge with 39SF010 + 74HCT00

Postby paulb » Wed Mar 15, 2017 10:19 pm

myelin wrote:As I wait for my Plus 1 to make its way across the Atlantic to San Francisco, I'm making hardware project plans :)

I have a Scarab miniSpartan6+ FPGA board (Spartan 6 LX25) on the way, but wanted to start out with something a bit simpler. An SST39SF010 128kx8 flash chip plus a 74HCT00 quad NAND gate to convert phi1/RnW/nOE into nWR, nOE, and nCE, should make for a very cheap (US$3.50 including PCB) and convenient two-bank/32kB flash cartridge for the Electron. I have a bunch of prototype boards sitting around, including an STM32F4 DISCOVERY, with which I should be able to make a cartridge programmer/interface. I'll post more details in this thread!


It looks like the flash memory is a variant of the Am29F010 which I got working with a dual ROM adapter. I tried to get it working with a more straightforward circuit and a prototyping cartridge, but I think that I may have experienced timing issues. If you figure something out, it would be interesting to see what you did.

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myelin
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Re: Simple Electron flash cartridge with 39SF010 + 74HCT00

Postby myelin » Thu Mar 16, 2017 12:00 am

Glad to hear that there's some precedent here!

I've been poring over timing diagrams, and I think the SST39SF010 should be compatible with 6502 timings... the only thing I can see possibly not working is the hold time at the end of a read cycle, given that "PHI OUT" / "phi2" on the extension connector and cartridge slot appears to actually be phi1, which leads phi2 by up to 20ns. EDIT: this appears to be incorrect -- see Dave H's post later in this thread.

This means that the flash might be required to assert the data bus for max 30 ns after the rising edge of phi1. The SST39SF010 datasheet says tCHZ and tOHZ are max 20 ns for the -50 part, and max 25 ns for the -70 part, so this is probably not too far off -- I should make sure to buy the slower chips though!

The 74HCT00 will be connected up like this:

  • flash_nCE = !(!nOE and !phi1) EDIT: need to change this to !(!nOE and phi0)
  • flash_nOE = !RnW
  • flash_nWR = RnW

So:

  • nOE from Electron -> both inputs of NAND1
  • phi1 from Electron -> both inputs of NAND2 EDIT: just pass through phi0 instead
  • NAND1 and NAND2 outputs -> NAND3 -> nCE on the flash chip
  • RnW from Electron -> both inputs of NAND4 -> nOE on the flash chip
  • RnW from Electron -> nWR on the flash chip

That means /OE will be low whenever the Electron is doing a read, /WR will be low whenever the Electron is doing a write, and /CE will be low while the cartridge is selected and phi1 is low. Should hopefully get rid of any weirdness :)
Last edited by myelin on Fri Mar 17, 2017 5:35 pm, edited 1 time in total.
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Re: Simple Electron flash cartridge with 39SF010 + 74HCT00

Postby myelin » Thu Mar 16, 2017 7:29 am

Progress! It passes DRC, but the routing still needs to be tidied up quite a lot. I always forget how much work it's going to be to route a whole bus :)

paulb wrote:I tried to get it working with a more straightforward circuit and a prototyping cartridge, but I think that I may have experienced timing issues. If you figure something out, it would be interesting to see what you did.


Thank you for open sourcing the prototyping cartridge design! So glad I didn't have to deal with all the measurements to get the edge connector, holes, and board outline all correct.

2017-03-15 board just barely passing DRC.png
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Re: Simple Electron flash cartridge with 39SF010 + 74HCT00

Postby paulb » Thu Mar 16, 2017 1:45 pm

myelin wrote:Thank you for open sourcing the prototyping cartridge design! So glad I didn't have to deal with all the measurements to get the edge connector, holes, and board outline all correct.


Nice work! Dave H needs a lot of credit for making measurements available and generally blazing the trail, though. Are you using KiCad as well?

Could you characterise the nOE signal? The Acorn documentation (AppNote 014) is vague about this:

2 n0E - Output Enable : Input with CMOS levels
This is an active low signal during the PHI2 [edited from "PH12"] period of the system clock. It is intended to switch on the output buffers of memory devices in cartridges. It is not guaranteed to be high at other times.


Reading this again, it seems to me that this must be a combination of RnW and PHI2.

As for data validity, if I understand the AMD datasheet correctly, it looks like the "output hold time" after nCE, nOE go high is a helpful minimum of 0ns. The maximum time before the data outputs become invalid is given as 30ns for the slowest part.

So, if you were looking to lengthen the period of time that nCE, nOE are low, it seems that using PHI1 would be beneficial. The Synertek hardware manual gives "TH" in terms of PHI2 going low, and since there is a time difference "TR" between that and PHI1 going high again, the flash signals could be held low for TR which would hopefully give just enough time for the CPU to acquire the data.

A quick and dirty diagram:

Code: Select all

     Time (ns):  0-------------- 500------------ 1000-
   2 MHz cycle:  0               1               2 ...
          PHI1:  //-----\\_______//-----\\_______/ ...
          PHI2:  \_______//-----\\_______//-----\\ ...

Switch from write to read:

           RnW:  ________________/////-----------\ ...
           nOE:  ----------------\\\\\__________// ...
           CE#:  -----------------------\\_______/ ...
           OE#:  ----------------\\\\\___________/ ...
           WE#:  ________________/////-----------\ ...


It's interesting what you're saying about the nature of PHI2 and it becoming almost like PHI1 again because of the propagation delays. When you refer to PHI1 in your signal definitions, are you referring to what is labelled as PHI2, or is it a separately derived PHI1? I do start to wonder whether the propagation delays were actually introduced to make what we're attempting to achieve easier.

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danielj
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Re: Simple Electron flash cartridge with 39SF010 + 74HCT00

Postby danielj » Thu Mar 16, 2017 1:48 pm

Myelin's right - Phi2 on the edge connector isn't actually Phi2, it is Phi1. I certainly came up against this when trying to prototype a 1MHz bus :?

d.

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MartinB
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Re: Simple Electron flash cartridge with 39SF010 + 74HCT00

Postby MartinB » Thu Mar 16, 2017 3:41 pm

I did some Elk Eeprom Cartridge stuff without particularly busting my nuts....

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Re: Simple Electron flash cartridge with 39SF010 + 74HCT00

Postby myelin » Thu Mar 16, 2017 3:57 pm

paulb wrote:Nice work! Dave H needs a lot of credit for making measurements available and generally blazing the trail, though. Are you using KiCad as well?


Yep, definitely a team effort here :) I am indeed using Kicad.

Could you characterise the nOE signal? The Acorn documentation (AppNote 014) is vague about this:

2 n0E - Output Enable : Input with CMOS levels
This is an active low signal during the PHI2 [edited from "PH12"] period of the system clock. It is intended to switch on the output buffers of memory devices in cartridges. It is not guaranteed to be high at other times.


Reading this again, it seems to me that this must be a combination of RnW and PHI2.


I spent some time tracing through the Plus 1 schematic; what happens in there is a latch (IC6, 74LS175) saves the four low bits of any writes to &FE05, and IC7, IC8, IC9, and IC2 generate four enable signals. Working through the logic, what I found is:

- IC2 pin 3 feeds /OE on the Plus 1 ROM, and is active (low) when RnW = 1 and bank = 12 and A = &8000-&BFFF
- IC7 feeds /OE3, which maps to nOE2 on both cartridge slots, and is active (low) when bank = 13 and A = &8000-&BFFF
- IC10 pin 8 feeds /OE2, which maps to nOE on the second cartridge slot, and is active (low) when bank = 2 or 3, and A = &8000-&BFFF
- IC10 pin 6 feeds /OE4, which maps to nOE on the first cartridge slot, and is active (low) when bank = 0 or 1, and A = &8000-&BFFF

Note how none of these are gated with the clock, which means they might glitch while the CPU is updating the address bus, and they'll often be active when the CPU isn't actually doing a read or write. I think this is what the docs are talking about when they say it's not guaranteed to be high at other times!

It's interesting what you're saying about the nature of PHI2 and it becoming almost like PHI1 again because of the propagation delays. When you refer to PHI1 in your signal definitions, are you referring to what is labelled as PHI2, or is it a separately derived PHI1? I do start to wonder whether the propagation delays were actually introduced to make what we're attempting to achieve easier.


As danielj says, the signal that is described by Acorn's docs as PH12 (AN14 cartridge spec) and PHI OUT (AN15 expansion spec) is actually PHI1 from the CPU. EDIT: this appears to be incorrect -- see Dave H's post later in this thread.

Here's the logic I'm using to generate /CE, /OE, and /WR for the flash chip:

2017-03-16 enable logic.png


This should result in /OE=0 when RnW=1, /WR=0 when RnW=0, and /CE=0 when nOE=0 and PHI1=0, which I believe satisfies the flash's timing for both reads and writes.
Last edited by myelin on Fri Mar 17, 2017 5:36 pm, edited 1 time in total.
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Re: Simple Electron flash cartridge with 39SF010 + 74HCT00

Postby paulb » Thu Mar 16, 2017 4:35 pm

MartinB wrote:I did some Elk Eeprom Cartridge stuff without particularly busting my nuts....


Yes, I saw that before, but /ROMOE in your diagram, which I guess is nOE in the documentation, didn't seem to be enough to drive the nCE (or CE# or /CE) pin on this kind of flash memory. Even though the pinouts are the same, I'm not sure that the behaviour is the same.

Then again, it is possible to drive this kind of IC from the Dual ROM Adaptor. According to the schematics for that, nCS (or CS# or /CS) is driven by RnW (actually CSRW as given by the AppNote, but that's supposedly the same thing as RnW on the Electron, despite the "chip select" naming), but then I can't see how this would work for reading from the memory at all.

The vague wording of the documentation is a real problem. It isn't possible to actually know what you're getting without looking at the schematic.

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Re: Simple Electron flash cartridge with 39SF010 + 74HCT00

Postby daveejhitchins » Thu Mar 16, 2017 4:39 pm

Regarding the Electron's Theta 1 vs Theta II signal - I've never had, in how many years :shock: , an issue with the wrong signal being used by the electron. I've not ever had to use a 'delay' - and I've literally thousands of product, in the field! I know all the arguments, for and against, however, BITD we (at Baildon electronics) carried out all sorts of testing with and without a delay and found no difference in the operation of any product plugged in to the cartridge socket [-( - So, please, take this information just as information . . . I'm not saying you shouldn't have the delay!

Hope this is of use to someone?

Dave H :D

If it would be of assistance (?) I can post the GAL equations that I used in the MGC. This uses the Am29F032B flash ROM.
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Re: Simple Electron flash cartridge with 39SF010 + 74HCT00

Postby myelin » Thu Mar 16, 2017 4:50 pm

daveejhitchins wrote:If it would be of assistance (?) I can post the GAL equations that I used in the MGC. This uses the Am29F032B flash ROM.


I'd love to see those, if you don't mind -- that would be an excellent data point! Glad to hear you haven't had any issues with clock timing either; that's reassuring :)
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Re: Simple Electron flash cartridge with 39SF010 + 74HCT00

Postby paulb » Thu Mar 16, 2017 4:52 pm

myelin wrote:I spent some time tracing through the Plus 1 schematic; what happens in there is a latch (IC6, 74LS175) saves the four low bits of any writes to &FE05, and IC7, IC8, IC9, and IC2 generate four enable signals. Working through the logic, what I found is:

- IC2 pin 3 feeds /OE on the Plus 1 ROM, and is active (low) when RnW = 1 and bank = 12 and A = &8000-&BFFF
- IC7 feeds /OE3, which maps to nOE2 on both cartridge slots, and is active (low) when bank = 13 and A = &8000-&BFFF
- IC10 pin 8 feeds /OE2, which maps to nOE on the second cartridge slot, and is active (low) when bank = 2 or 3, and A = &8000-&BFFF
- IC10 pin 6 feeds /OE4, which maps to nOE on the first cartridge slot, and is active (low) when bank = 0 or 1, and A = &8000-&BFFF

Note how none of these are gated with the clock, which means they might glitch while the CPU is updating the address bus, and they'll often be active when the CPU isn't actually doing a read or write. I think this is what the docs are talking about when they say it's not guaranteed to be high at other times!


Yes, the vagueness of the documentation is just superb here. I was actually going through the schematics to trace the different output enable signals, so you've saved me quite a bit of effort. Thank you for this summary!

It certainly makes sense to combine nOE with "PHI2" (really PHI1), and other tests I've done have employed the clock signal for reads and writes using 7400-series logic ICs with a degree of success.

myelin wrote:As danielj says, the signal that is described by Acorn's docs as PH12 (AN14 cartridge spec) and PHI OUT (AN15 expansion spec) is actually PHI1 from the CPU.


Looking at a bad photocopy of the Plus 1 schematic I found once, it appears that PHI OUT (labelled as PHI0) just goes straight through to the cartridge slots.

myelin wrote:Here's the logic I'm using to generate /CE, /OE, and /WR for the flash chip:

2017-03-16 enable logic.png

This should result in /OE=0 when RnW=1, /WR=0 when RnW=0, and /CE=0 when nOE=0 and PHI1=0, which I believe satisfies the flash's timing for both reads and writes.


I shall have to look at this again at some point, but your logic seems sound. Thanks for looking into the circuit behaviour!

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Re: Simple Electron flash cartridge with 39SF010 + 74HCT00

Postby myelin » Thu Mar 16, 2017 5:29 pm

paulb wrote:
MartinB wrote:I did some Elk Eeprom Cartridge stuff without particularly busting my nuts....


Yes, I saw that before, but /ROMOE in your diagram, which I guess is nOE in the documentation, didn't seem to be enough to drive the nCE (or CE# or /CE) pin on this kind of flash memory. Even though the pinouts are the same, I'm not sure that the behaviour is the same.


This is really interesting... looking at the datasheet for the AT28C256, which MartinB used, it has the same write timings as the SST39SF010, i.e. you need to keep /OE high and bring both /CE and /WR low to write a byte, and the address gets latched on the latest falling edge (i.e. if you bring /CE low, then a bit later bring /WR low, the address gets latched on the falling edge of /WR), then the data gets latched on the first rising edge.

Here's what I suspect is happening: the 6502 starts out executing from RAM, so the initial state is RnW=1 and A != &8000-&BFFF, which means nOE=1 and RnW=1 on the cartridge connector. When the 6502 starts the write cycle, it'll set RnW=0 around the same time the address bus gets set up. This will result in a high-to-low transition on /CS and /WE on your flash chip, and a low-to-high transition on /OE, which all might be glitchy, but if the flash is forgiving or RnW goes low a little after the address is set up, it latches the address correctly. At the end of the write cycle, the datasheet suggests that the address and RnW will be held longer than the data, but if the 6502 actually holds the data valid much longer than that, or there's a lot of capacitance in the data bus, the data stays valid for long enough for it to be latched on the address + RnW transition later in the cycle.

It's the sort of thing that looks like it should never work from reading the timing diagrams, but Martin's experience would suggest otherwise :D
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Re: Simple Electron flash cartridge with 39SF010 + 74HCT00

Postby daveejhitchins » Thu Mar 16, 2017 5:50 pm

Again, if it's of interest . . . The ABR can take an AT28C256 without serious modification (just removal of the battery), however, where the ABR differs, from MartinB's use, is in the Locking mechanism - which is an electronic version of Martin's write protect link. If you are using a PLD, for the decoding logic, it's easy to add the Lock code. And there's plenty of utilities around that support it.

Dave H :D
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Re: Simple Electron flash cartridge with 39SF010 + 74HCT00

Postby daveejhitchins » Thu Mar 16, 2017 6:12 pm

Here's the equations for the MGC:

Code: Select all

Name     Mega Games Cartridge IC2 ;
PartNo   IC2 ;
Date     28/07/2015 ;
Revision 04 ;
Designer Dave Hitchins ;
Company  Retro Hardware ;
Assembly None ;
Location IC2 ;
Device   g22v10 ;
/* 01-02-15 Issue 2 - Corrected address for Clk1 and 2 (swapped!)            */
/* 08-04-15 Issue 3 - Inverted QA in A21 to place 0 page in higher ROM slot  */
/* 28-07-15 Issue 4 - Removed !nOE from RnOE, leaving ONLY EMRnW        */
/*                  - Added T2 to nW                    */
/* *************** INPUT PINS ************************************************/
PIN 1   = DCK1     cc                     ; /* Delayed Clock from Pin 23       */
PIN 2   = nOE                           ; /* Electron slot nOE               */
PIN 3   = nRST                          ; /* System Reset - All outputs to 0 */
PIN 4   = T2                            ; /* CPU Clock                       */
PIN 5   = EMRnW                         ; /* Elektron / Master Read notWrite */
PIN 7   = nPFC                          ; /* Not Page &FC                    */
PIN 8   = A3                            ; /* Address line A3                 */
PIN 9   = D1                            ; /* Data 1                          */
PIN 10  = D2                            ; /* Data 2                          */
PIN 11  = D0                            ; /* Data 0                          */

PIN 13  = nA4567                        ; /* (A4+A+A6+A7) from IC3           */
PIN 14  = QA                            ; /* Electron slot Bank select       */
/* *************** OUTPUT PINS ***********************************************/
PIN 15  =  A21                          ; /* Address line 21 to ROM          */
PIN 16  = !RnOE                         ; /* ROM Not Output Enable           */
PIN 17  =  RPM                          ; /* Page Mode (internal only)       */
PIN 18  =  RBS                          ; /* Bank Select (internal only)     */
PIN 19  = !RnCE                         ; /* ROM Not Chip Enable             */
PIN 20  =  RWE                          ; /* Write Enable (internal only)    */
PIN 21  =  CKO2                         ; /* Clock output to IC3 pin 1       */
PIN 22  = !nW                           ; /* ROM Not Write                   */
PIN 23  =  CKO1                         ; /* Clock Output to Pin 1           */

/* **************** EQUATIONS ************************************************/

A21     = !RPM & !QA
        #  RPM &  RBS                   ; /* Address line 21 to ROM          */
/* A21=Bank Select. With PM=L A21 is controlled by QA 'slot bank selector'   */
/*                  With PM=H A21 is controlled by BS 'Bank Select' -        */
/*                     Always in the higher ROM number - Controlled by RnCE  */

RWE.D    =  D0                          ; /* Write Enable L=Inhibit H=Enable */
RWE.AR   = !nRST                        ; /* Main CPU Reset - Sets Output=L  */
RWE.OE   = 'b'1                         ; /* Always enabled                  */
RWE.SP   = 'b'0                         ; /* Never preset                    */

RBS.D    =  D1                          ; /* Bank Select L=LowRom H=HighROM  */
RBS.AR   = !nRST                        ; /* Main CPU Reset - Sets Output=L  */
RBS.OE   = 'b'1                         ; /* Always enabled                  */
RBS.SP   = 'b'0                         ; /* Never preset                    */

RPM.D    =  D2                          ; /* Page Mode L=2Pages H=1Page      */
RPM.AR   = !nRST                        ; /* Main CPU Reset - Sets Output=L  */
RPM.OE   = 'b'1                         ; /* Always enabled                  */
RPM.SP   = 'b'0                         ; /* Never preset                    */

RnOE    = EMRnW                         ; /* Not Output enable to ROM        */
/* Master or Electron R/nW - Selected by SN74LVC97, one of two decoder       */

RnCE    = !RPM & T2 & !nOE
        #  RPM & T2 & !nOE &  QA        ; /* Not Chip enable to ROM          */
/* ROM nCE active when (PM=L AND QA=L OR QA=H) OR (PM=H AND QA=H)            */

nW      =  RWE & !EMRnW & T2            ; /* Not Write to ROM                */
/* Writes to ROM controlled by WE - WE default=L Inhibit                     */

CKO2    = !nPFC & !nA4567 & !A3 & !EMRnW  & T2
                                        ; /* Clock to Pin 1 IC3 - Write only */
/* Address for ROM Address Latch=&FC00 to &FC07 - Gated with T2              */

CKO1    = !nPFC & !nA4567 &  A3 & !EMRnW  & T2
                                        ; /* Clock to Pin 1 IC2 - Write only */
/* Address for Control Latch=&FC08 to &FC0F - Gated with T2                  */


Code: Select all

Name     Mega Games Cartridge IC3 ;
PartNo   IC2 ;
Date     06/01/2015 ;
Revision 01 ;
Designer Dave Hitchins ;
Company  Retro Hardware ;
Assembly None ;
Location IC3 ;
Device   g22v10 ;

/* *************** INPUT PINS ************************************************/
PIN 1   = DCK2                    ; /* Delayed Clock from IC2                */
PIN 2   = NRST                    ; /* System Reset - All outputs to 0       */
PIN 3   = D7                      ; /* Data 7                                */
PIN 4   = D6                      ; /* Data 6                                */
PIN 5   = D5                      ; /* Data 5                                */
PIN 6   = D4                      ; /* Data 4                                */
PIN 7   = D3                      ; /* Data 3                                */
PIN 8   = D0                      ; /* Data 0                                */
PIN 9   = D1                      ; /* Data 1                                */
PIN 10  = A4                      ; /* Address line 4                        */
PIN 11  = D2                      ; /* Data 2                                */

PIN 13  = A5                      ; /* Address line A5                       */
PIN 22  = A6                      ; /* Address line A6                       */
PIN 23  = A7                      ; /* Address line A7                       */

/* *************** OUTPUT PINS ***********************************************/
PIN 14  = !A4567                  ; /* (A4+A5+A+A7) to IC3                   */
PIN 15  =  RA20                   ; /* Address line 20 to ROM                */
PIN 16  =  RA19                   ; /* Address line 19 to ROM                */
PIN 17  =  RA18                   ; /* Address line 18 to ROM                */
PIN 18  =  RA17                   ; /* Address line 17 to ROM                */
PIN 19  =  RA16                   ; /* Address line 16 to ROM                */
PIN 20  =  RA15                   ; /* Address line 15 to ROM                */
PIN 21  =  RA14                   ; /* Address line 14 to ROM                */

/* **************** EQUATIONS ************************************************/

RA14.D  =  D0                     ; /* Address line 14 to ROM                */
RA14.AR = !NRST                   ; /* Main CPU Reset - Sets Output=L        */
RA14.OE = 'b'1                    ; /* Always enabled                        */
RA14.SP = 'b'0                    ; /* never preset                          */

RA15.D  =  D1                     ; /* Address line 15 to ROM                */
RA15.AR = !NRST                   ; /* Main CPU Reset - Sets Output=L        */
RA15.OE = 'b'1                    ; /* Always enabled                        */
RA15.SP = 'b'0                    ; /* never preset                          */

RA16.D  =  D2                     ; /* Address line 16 to ROM                */
RA16.AR = !NRST                   ; /* Main CPU Reset - Sets Output=L        */
RA16.OE = 'b'1                    ; /* Always enabled                        */
RA16.SP = 'b'0                    ; /* never preset                          */

RA17.D  =  D3                     ; /* Address line 17 to ROM                */
RA17.AR = !NRST                   ; /* Main CPU Reset - Sets Output=L        */
RA17.OE = 'b'1                    ; /* Always enabled                        */
RA17.SP = 'b'0                    ; /* never preset                          */

RA18.D  =  D4                     ; /* Address line 18 to ROM                */
RA18.AR = !NRST                   ; /* Main CPU Reset - Sets Output=L        */
RA18.OE = 'b'1                    ; /* Always enabled                        */
RA18.SP = 'b'0                    ; /* never preset                          */

RA19.D  =  D5                     ; /* Address line 19 to ROM                */
RA19.AR = !NRST                   ; /* Main CPU Reset - Sets Output=L        */
RA19.OE = 'b'1                    ; /* Always enabled                        */
RA19.SP = 'b'0                    ; /* never preset                          */

RA20.D  =  D6                     ; /* Address line 20 to ROM                */
RA20.AR = !NRST                   ; /* Main CPU Reset - Sets Output=L        */
RA20.OE = 'b'1                    ; /* Always enabled                        */
RA20.SP = 'b'0                    ; /* never preset                          */

A4567   = !A4 & !A5 & !A6 & !A7   ; /* When A4, A5, A6, A7 = 0  Out=0        */

and the schematic, Note: not in the schematic or in the above equations, as yet, R1 & R2 have effectively been replaced with links and CK01 and CK02 outputs have been inverted.
MGC Schematic 6-1-15.JPG


Dave H :D
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Re: Simple Electron flash cartridge with 39SF010 + 74HCT00

Postby MartinB » Thu Mar 16, 2017 6:59 pm

myelin wrote:It's the sort of thing that looks like it should never work from reading the timing diagrams, but Martin's experience would suggest otherwise :D

When it comes to the Elk, my only use for textbooks is to wedge wobbly prototypes in place in the Plus 1 cartridge slots. Anything else and the Elk will simply mock you.... :lol:

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Re: Simple Electron flash cartridge with 39SF010 + 74HCT00

Postby paulb » Thu Mar 16, 2017 10:10 pm

daveejhitchins wrote:Here's the equations for the MGC:


Thanks, Dave! I guess that if we take these definitions...

Code: Select all

PIN 2   = nOE                           ; /* Electron slot nOE               */
PIN 4   = T2                            ; /* CPU Clock                       */
PIN 17  =  RPM                          ; /* Page Mode (internal only)       */
PIN 19  = !RnCE                         ; /* ROM Not Chip Enable             */


...in the context of this equation...

Code: Select all

RnCE    = !RPM & T2 & !nOE


...and if we ignore the page mode thing, which is presumably the special feature of the MGC that allows different banks to be selected, then we get...

Code: Select all

RnCE    = T2 & !nOE


...which is rewritten in the terms used elsewhere as...

Code: Select all

!nCE = PHI and !nOE


So we then get...

Code: Select all

nCE = !(PHI and !nOE)


If you'll forgive another quick and dirty diagram:

Code: Select all

     Time (ns):  0-------------- 500------------ 1000---- ...
   2 MHz cycle:  0               1               2        ...
          PHI1:  //-----\\_______//-----\\_______//-----\ ... ("PHI2" in the documentation")

      not PHI1:  \\_____//-------\\_____//-------\\_____/ ...

                 write cycle     read cycle      write cycle

           RnW:  ________________/////-----------\\\\\___ ...
     Addresses:  XXXXX===========XXXXX===========XXXXX=== ...
           nOE:  ----------------\\\\\___________/////--- ...

       not nOE:  ________________/////-----------\\\\\___ ...

not nOE and PHI1:
                 ________________/////--\\_______/////--\ ...

           CE#:  -----------------------\\_______/////--- ...
           OE#:  ----------------\\\\\___________/////--- ...
           WE#:  ________________/////-----------\\\\\--- ...


Here, we see that the waveform for this equation appears to achieve the CE# (or nCE, /CE, and so on) transition from high to low (illustrated at the end). If used to drive CE# it will also hold CE# low at other times (see the write cycle).

On the crude scale employed above, each character is around 31.25ns, and uncertainties are marked with repeated / or \ symbols. The Synertek hardware manual gives uncertainties for the 1MHz parts, so it's possible that they are overstated above.

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Re: Simple Electron flash cartridge with 39SF010 + 74HCT00

Postby myelin » Fri Mar 17, 2017 12:51 am

daveejhitchins wrote:Here's the equations for the MGC:


This is fascinating! Is there an inversion happening somewhere, or is your T2 really the system clock (PHI1)? It looks like you're gating nCE and nW so that they're both disabled (!RnCE=1, !nW=1) when T2=0. Given the timing info I've seen, it looks like this should result in spurious pulses on nW, and the flash chip being entirely disabled when the 6502 is trying to read from it. I'm starting to think I have everything backwards with the clock...
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Re: Simple Electron flash cartridge with 39SF010 + 74HCT00

Postby daveejhitchins » Fri Mar 17, 2017 8:15 am

Well, let's look at what we're using . . .

Here's part of the Electron schematic:
Elk Clock.png

Notice where Theta Out, on the edge connector is fed from!

6502 Timeing:
timing.png
Not Theta 1 or Theta 2 but Theta 0 the 6502 clock input!

Does that make more sense?

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Re: Simple Electron flash cartridge with 39SF010 + 74HCT00

Postby 1024MAK » Fri Mar 17, 2017 8:30 am

How much difference using the different clock signals makes, very much depends on if the correct gating of the control signals is done, and the access delay of the RAM/ROM/IO ICs is quick enough. The remaining factor is when the 6502 samples the data bus during a read operation. Without doing a lot of experiments, this is difficult to determine. If the 6502 is late in sampling and the capacitance of the bus is poor, the 6502 could read invalid data. But in practice, if the CPU input clock goes through two or three gates, this is unlikely to be a problem.

The only practical problems that I am aware of is some data corruption when using SRAM on some cartridges with some Plus 1 units.

It is entirely possible that the clock outputs from the 6502 are just buffered (and inverted) versions of the clock input. So the difference is just the propagation delay of the internal buffer(s).

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Re: Simple Electron flash cartridge with 39SF010 + 74HCT00

Postby jms2 » Fri Mar 17, 2017 12:53 pm

daveejhitchins wrote:Does that make more sense?


That's a very helpful post Dave, because for me it does clear up the confusion. It was previously stated (higher up in this thread and also in the linked thread) that the signal available at the cartridge sockets was Phi1. What you've demonstrated is that it is actually Phi0. [And, to be pedantic, it is Phi by the way, not theta, although the greek letters do look similar! :D ]

For the explanation of the difference between the clock signals, have a look here.. And for interfacing to memory, I found this link interesting.

So in terms of how this works on the Electron, my summary is:

1) The Elk outputs Phi0, not Phi2. This is technically a bit wrong, but it doesn't cause a major problem (at least not for memory access - the first of my links above suggest it is important when interfacing with 6522s, and I think MartinB found similar issues with EUP.)
2) The Plus 1 sends this signal straight out to the cartridge slots.
3) The Plus 1 OE signal is not gated with Phi0 (or any other clock signal), you have to do this yourself.

This all reminds me, I need to finish off the Elk AUG. There is probably something in the above that ought to be included.

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Re: Simple Electron flash cartridge with 39SF010 + 74HCT00

Postby MartinB » Fri Mar 17, 2017 3:06 pm

Just to clarify the position regarding EUP.....

My original EUP design, which was predicated on adding a 6522 User Port to the Elk/Plus 1 combo, did (does) include a passive delay in Phi before the latter is used in the 6522 access logic. It is important to note that all the 6522 functional aspects have always worked perfectly from day one for all users of EUP in whatever host configuration.

EUP Phi.png


When I decided to also add sideways rom and ram support, I only used the Acorn-provided cartridge control signals since these were specifically designed to allow memory access through the cartridge ports and theoretically therefore shouldn't need to be modified. Throughout all my development work using three Elks, three Plus 1's and a Rombox, I never had (and still haven't to this today) had any problems with reading or writing any memory devices.

There were however a number of EUP users, let's say a third, who were experiencing sideways ram corruptions after loading and it was only in the course of investigating this issue that I started playing with additional gating of the cartridge signals and tinkering with the Phi delay. At the end of the day, I devised a mod (effectively gating RnW with the delayed Phi) which sorted the corruptions for about one half of the affected third but there were I believe a residual few who still reported an occasional glitch.

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Re: Simple Electron flash cartridge with 39SF010 + 74HCT00

Postby myelin » Fri Mar 17, 2017 5:33 pm

myelin wrote:I'm starting to think I have everything backwards with the clock...

daveejhitchins wrote:Not Theta 1 or Theta 2 but Theta 0 the 6502 clock input!

Does that make more sense?


It does indeed -- thank you Dave! I've had it backwards (well, inverted...) this whole time :lol:

I'm glad I moved the traces on my cartridge PCB design last night to make it possible for me to un-invert the clock! The design is with the fab (makerstudio.cc, good and cheap if you're ok waiting 3 weeks to get your boards) now -- looking forward to being able to build it up and test it.

Time to go clear up this misconception elsewhere as well, and edit my old posts so I don't lead anyone else astray :)

Re-analyzing memory timings in light of this new revelation, with all timings relative to Phi0:

When the 6502 is doing a read:

The address is set up during the Phi2 low period, and is valid by tDLY + tADS = 50+100 = 150 ns after the falling edge of Phi0. For a 250ns pulse width at 2MHz, that means the address is valid for 100ns before the rising edge of Phi0. The 6502 needs data to be valid from 100ns before the Phi2 falling edge to 10ns after, i.e. 50ns before the Phi0 falling edge and 60ns after.

The address remains valid until 15ns after the Phi2 falling edge, i.e. 65ns after the Phi0 falling edge.

When the 6502 is doing a write:

As above, the address is valid 100ns before the rising edge of Phi0. The data is valid from tWDS = 110ns after the rising edge of Phi2 until tHW = 30ns after the falling edge, i.e. from 160ns after the rising edge of Phi0 to 80ns after the falling edge.

Summary:

Don't do anything while Phi0 is low :)

If you're making a device that accepts reads from the 6502, you can count on the address being valid from 100ns before the rising edge of Phi0 to 60ns after the falling edge, and you need to make the data available by 10ns before the falling edge and hold it for 60ns after the falling edge.

The 60ns hold time requirement might cause issues; I know the SST39SF010A doesn't guarantee to hold its outputs that long.

If you're making a device that accepts writes from the 6502, the address will be valid as above, and the data will be valid from 160ns after the rising edge of Phi0 to 80ns after the falling edge.

This will work fine as long as your device waits for the falling edge to sample the data bus, and doesn't expect the data to be valid at the start of the pulse. Most memory chips work this way. If you're using something level triggered, you'll need to do something clever to stop your device from reading the bus before it's been set up.
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Re: Simple Electron flash cartridge with 39SF010 + 74HCT00

Postby paulb » Sun Mar 19, 2017 11:38 pm

OK, I got to try this again with the Am29F010 flash memory, and with Dave H's formula for CE# it was a lot more successful.

I had a look at the timings again and found a few mistakes in what I posted before, so here's my current understanding:

Code: Select all

     Time (ns):  0-------------- 500------------ 1000------ ...
   2 MHz cycle:  0               1               2          ...
          PHI0:  /-------\_______/-------\_______/-------\_ ... ("PHI2" in the Plus 1 documentation)
          PHI2:  __/-------\_______/-------\_______/------- ... approximate delay from PHI0
          PHI1:  -\_______/-------\_______/-------\_______/ ... approximate delay from PHI0

      not PHI0:  \_______/-------\_______/-------\_______/- ...

                 -------- read----------- write---------- r ...
    PHI1 cycle:           0               1               2 ...

           RnW:  _________//--------------\\______________/ ...
     Addresses:  =========XX==============XX==============X ...
     Data read:           XXXXXXXXXXXX<<=====>>             ...
    Data write:  XXXXXX<<====>>           XXXXXXXXXXXXX<<== ...
           nOE:  ---------\\______________//--------------\ ...

       not nOE:  _________//--------------\\______________/ ...

not nOE and PHI0:________________/-------\_________________ ...
nOE or not PHI0: ----------------\_______/----------------- ...

           CE#:  ----------------\_______/----------------- ... (nOE or not PHI0)
           OE#:  ---------\\______________//--------------- ... (not RnW)
           WE#:  _________//--------------\\_______________ ... (RnW)


I've tried to incorporate things like address and data stability in this illustration. What Dave H does for the MGC is to combine nOE with PHI0:

Code: Select all

nCE = !(PHI and !nOE)


This is equivalent to the following from the above (applying De Morgan's laws):

Code: Select all

CE# = nOE or not PHI0


The result is CE# being brought low in the desired time period, albeit later than OE# and WE#, which you usually don't see in timing diagrams for these ICs.

Previously, I'd misused &FC73 and nROMSTB for paging, but to avoid any software complications and to do things by the book, I switched to using &FC80 and a decoder (74HC138) to set persistent values for A15 and A16 in a flip-flop (74HC273). With the above CE# formula in use, I managed to load the games that davidb had flashed to the memory. Switching to using the following brought back the old unreliability I first encountered:

Code: Select all

CE# = nOE


(I tried combining nOE with other things, but not PHI0 if I recall, to no avail previously.)

Returning to the Dave H formula, and everything seemed to work again. Personally, I'm a lot more satisfied with this now, and thanks must go to Dave H for having figured this out, it possibly being significant for these AMD parts. Apologies to myelin for not having come to this conclusion sooner!

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Re: Simple Electron flash cartridge with 39SF010 + 74HCT00

Postby myelin » Mon Mar 20, 2017 12:42 am

Nice diagram paulb! Looks like you've verified the circuit that's on my simple flash board (once I cut the trace on it and solder in a wire to allow for "PHI" being phi0 and not phi1), so that's promising.

My employer makes employees jump through some hoops before releasing anything as open source, but once I've taken care of the paperwork, I'll release my flash cart design files (based on yours, so GPL3). Today I'm going to start on a breakout board like yours but for the rear expansion connector, so I can try some ideas that'll work without a Plus 1.
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Re: Simple Electron flash cartridge with 39SF010 + 74HCT00

Postby paulb » Mon Mar 20, 2017 1:02 am

myelin wrote:Nice diagram paulb! Looks like you've verified the circuit that's on my simple flash board (once I cut the trace on it and solder in a wire to allow for "PHI" being phi0 and not phi1), so that's promising.

My employer makes employees jump through some hoops before releasing anything as open source, but once I've taken care of the paperwork, I'll release my flash cart design files (based on yours, so GPL3). Today I'm going to start on a breakout board like yours but for the rear expansion connector, so I can try some ideas that'll work without a Plus 1.


I appreciate your efforts with the paperwork, although I feel a bit bad that I might somehow be making you jump through such hoops. Really, I'm just aiming for a share-alike licence, and I did update the documentation yesterday to clarify a few things, indicating that I don't expect people to put my name on their boards forever more (which was a possible assumption of their obligations based on general licensing practices).

There are arguments that copyright licences aren't that great for hardware, but something like a circuit board is pretty much like a drawing, and so I don't see why, say, Creative Commons licensing is acceptable for hardware and other licences are not. Nevertheless, I'm open to suggestions. What I want to achieve is a situation where people can get a board and then be able to make their own version and for the designs to always be free (as in liberated). Proprietary boards are so 1980s, and they weren't a good idea back then, either.

I like the idea of an expansion bus breakout, and I have also contemplated an extender card for prototyping, so it will be interesting to see what you come up with.

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Re: Simple Electron flash cartridge with 39SF010 + 74HCT00

Postby myelin » Mon Mar 20, 2017 8:39 pm

paulb wrote:I appreciate your efforts with the paperwork, although I feel a bit bad that I might somehow be making you jump through such hoops. Really, I'm just aiming for a share-alike licence, and I did update the documentation yesterday to clarify a few things, indicating that I don't expect people to put my name on their boards forever more (which was a possible assumption of their obligations based on general licensing practices)


It's no big deal really; it just means I can't throw random things on github without sending in a form at work :)

In other news, I've been playing with a Xilinx XC9572XL CPLD board and finally have it coming up and programming correctly. Looking forward to playing with this once the prototype boards show up. I'm pretty sure it has enough room in it to implement stuff like RS232 and SPI ports, which could make for a nice simple user port / SD card interface.
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Re: Simple Electron flash cartridge with 39SF010 + 74HCT00

Postby myelin » Fri Apr 07, 2017 11:13 pm

Look what arrived today! (Plus a batch of PaulB's breakout boards).
32kb_flash_cartridge_pcb_1000px.jpeg
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Re: Simple Electron flash cartridge with 39SF010 + 74HCT00

Postby paulb » Fri Apr 07, 2017 11:28 pm

myelin wrote:Look what arrived today! (Plus a batch of PaulB's breakout boards).


Very nice! Interesting how the "keep out" areas are marked, though. Either I can't see that in the disappointingly dark purple that OSHPark actually deliver or that layer information made its way into the Gerbers for you but not for me. Good luck with the next part of the exercise!

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Re: Simple Electron flash cartridge with 39SF010 + 74HCT00

Postby myelin » Tue Apr 18, 2017 8:01 am

And... it works!

Took a while to write the programmer code, especially as the whole thing had to be in assembly, but the signalling seems to be nice and solid. I managed to program a Hopper ROM into bank 0, and boot and run it, and just got Starship Command (which has two 16kB ROM images, so was a bit more complicated) working.

I ran into issues with the Electron getting really unstable (looping on boot), which seem to be because the ULA was overheating. Opening up the case and giving it a chance to cool down seemed to fix it. Is this a common problem?
SW/EE from New Zealand, now in San Francisco: http://myelin.nz/
Having fun making hardware projects for the Electron!
So far: 32k flash cart, USB cart interface, 3-cart expansion, Elk PiTubeDirect. Later: Dual ported ram cart.


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