dominicbeesley wrote:I've ordered that spartan board, I couldn't find much documentation about how the level shifter board works or how to map the pins onto that Spartan Board....no doubt I'll be back with questions when the parts arrive....
I don't think Jason ever posted the schematics.
Probably the best starting point is one of the existing .ucf files:
https://github.com/hoglet67/AtomBusMon/ ... /board.ucf
dominicbeesley wrote:Is there something Xilinx specific or would it just be the usual faff of setting up the project in Quartus instead of Xise?
It's mostly just the usual faff.
There is one large 512x72 FIFO (called WatchEvents) that was created using the Xilinx Core Gen tool, so that all that would need to be replaced.
The tool chain is a bit more complicated than a pure FPGA because the design includes a support processor (a soft AVR) whose C code needs to be compiled and converted to block RAM initialization data. I built a set of makefiles to do the C compile, the Xilinx compile, and then link everything together. It would be quite fiddly to add Altera into the mix, but possible if there was some interest.
Beeb FPGA actually embeds ICE T65 (with a pre-compiled version of the C code) in the Altera DE1 build, so it has been built on Altera. So all the bits exist.
I don't have a DE0 Nano myself, so it would be a bit hard for me to test this.