Beeb FPGA

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dominicbeesley
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Re: Beeb FPGA

Postby dominicbeesley » Mon Sep 04, 2017 10:56 am

HDMI can be coaxed out of the de0 nano so should be doable from the de1. I got it working with my BeebFPGA I did a few years ago I think I started with something from here http://hamsterworks.co.nz/mediawiki/ind ... nimal_HDMI but can't quite find the exact project I cribbed. I seem to recall the clever bit was getting the dual phase clocks working.

It wasn't that much use in the end though, unless you added a frame buffer and output at 100Hz, many monitors (including my Dell and Iyama) see 50Hz frame rate as invalid (American/Japanese chauvanism!) so my simple line doubling experiments only worked if I ran the beeb at 60Hz instead of 50 make games a bit too fast.

I'll dig out the code if there's interest, I can't remember the exact details of the lead I made but I think it was pretty simple, not to HDMI spec but it ran fine on a 1m length connected up to the balanced LV outputs of the DE0 nano.

If you run into problems with interrupts let me know, I think I was using the t65 core and is has a bug that shows up in certain interrupt situations (I can't remember the ins and outs but it was a simple one line fix)

D

vanfanel
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Re: Beeb FPGA

Postby vanfanel » Fri Sep 08, 2017 12:16 pm

@hoglet: page turned so maybe you didn't see my message... Any news or ideas on the "Speech!" problems with the core, please?
I'd like to demo it here in spain, and this program would be awesome to show what the BBC Micro was capable of!

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tricky
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Re: Beeb FPGA

Postby tricky » Fri Sep 08, 2017 12:33 pm

I can't think why this might affect speech!, but sample playing routines from the NES don't work on the beeb as the sn76489 seems to be subtly different (jsbeeb implements the kind usually found in a nes) this only really affects frequency timer value 0, so I guess it's more about interrupt handling or slow databus handling.

Sorry if this is not helpful.

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fordp
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Re: Beeb FPGA

Postby fordp » Fri Sep 08, 2017 2:02 pm

dominicbeesley wrote:HDMI can be coaxed out of the de0 nano so should be doable from the de1. I got it working with my BeebFPGA I did a few years ago I think I started with something from here http://hamsterworks.co.nz/mediawiki/ind ... nimal_HDMI but can't quite find the exact project I cribbed. I seem to recall the clever bit was getting the dual phase clocks working.

It wasn't that much use in the end though, unless you added a frame buffer and output at 100Hz, many monitors (including my Dell and Iyama) see 50Hz frame rate as invalid (American/Japanese chauvanism!) so my simple line doubling experiments only worked if I ran the beeb at 60Hz instead of 50 make games a bit too fast.

I'll dig out the code if there's interest, I can't remember the exact details of the lead I made but I think it was pretty simple, not to HDMI spec but it ran fine on a 1m length connected up to the balanced LV outputs of the DE0 nano.

If you run into problems with interrupts let me know, I think I was using the t65 core and is has a bug that shows up in certain interrupt situations (I can't remember the ins and outs but it was a simple one line fix)

D

Strange that as all proper HDMI monitors must support 576p and 576i. I am not sure if the pixels on the beeb can fit on a 576i mode with 1:1 pixels however?
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dominicbeesley
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Re: Beeb FPGA

Postby dominicbeesley » Fri Sep 08, 2017 2:36 pm

Nope, Take this one at random (first one I found) http://www.dell.com/downloads/emea/prod ... onitor.pdf

Most tellies say they do 576i/50, all my monitors wont! I've no idea why, I find it particularly annoying! I suspect its to stop us all from using (cheap) monitors instead of more expensive TV's

It would be ok if they'd 576p even, at least line doubling doesn't need a whole frame buffer...

If you find out different though let me know...

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hoglet
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Re: Beeb FPGA

Postby hoglet » Fri Sep 08, 2017 2:38 pm

vanfanel wrote:@hoglet: page turned so maybe you didn't see my message... Any news or ideas on the "Speech!" problems with the core, please?

Sorry, no.

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hoglet
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Re: Beeb FPGA

Postby hoglet » Mon Sep 11, 2017 4:25 pm

vanfanel wrote:@hoglet: page turned so maybe you didn't see my message... Any news or ideas on the "Speech!" problems with the core, please?

Actually, yes.

I've just switched to a different sn76489 model (from the pace project, Programmable Arcade Circuit Emulation) and that has resolved the issue with Speech!.

That change is now in github:
https://github.com/hoglet67/BeebFpga/commits/master

Dave
Last edited by hoglet on Thu Sep 14, 2017 8:02 pm, edited 1 time in total.

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fordp
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Re: Beeb FPGA

Postby fordp » Tue Sep 12, 2017 8:30 am

dominicbeesley wrote:Nope, Take this one at random (first one I found) http://www.dell.com/downloads/emea/prod ... onitor.pdf

Most tellies say they do 576i/50, all my monitors wont! I've no idea why, I find it particularly annoying! I suspect its to stop us all from using (cheap) monitors instead of more expensive TV's

It would be ok if they'd 576p even, at least line doubling doesn't need a whole frame buffer...

If you find out different though let me know...


I was reading up on 576i and it seems to imply that you can have a range of number of pixels per "scan line" and not just the 720 that is typical.

If you could have 640 pixels and 576i then no scan doubler should be required?
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dominicbeesley
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Re: Beeb FPGA

Postby dominicbeesley » Tue Sep 12, 2017 11:37 am

That's great but there are very few *monitors* that would work. Increasing the number of pixels on a line does not increase the number of times it is scanned per second, that would just up the pixel clock.

see the spec I posted:
Minimum horz freq 30kHz (i.e. Interlace will not work *1)
Minimum vert freq 56Hz (i.e. PAL refresh will not work *2)

*1 interlaced will not work at 50Hz: in 576i at 50Hz ~ 15kHz, [BTW 576 refers to *visible* lines, about 1/4 are retrace lines, the designers of digital decided to include the time required to reverse the spins of electrons in a pound of steel in the vertical output transformer in a 1930's telly and similar dead space on each line for line flyback!] There would still be 312.5*50 lines per second i.e. 15,625Hz - the PAL line frequency. If you output each line twice i.e. 576p (which is what I did) that gives 31,250Hz (in spec)

*2 Vertical refresh is still 50Hz (out of spec). Increasing that either requires upping the frame rate (which I did, but causes games to run ~20% fast) or doing a frame store so the FPGA 6845/ULA can do its thing at its own speed and we can output frames at a different speed. Frame doubling is probably the simplest and would give the most pleasing results (i.e. no tearing).

D

D

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fordp
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Re: Beeb FPGA

Postby fordp » Tue Sep 12, 2017 1:16 pm

My TV I use on my Beeb FPGA works on the VGA port with both scan doubling and at normal TV rates. The picture quality does vary a lot but I do get a picture. I must look in to HDMI more at some point as I know little about how it works. I know the the 576i/25 is meant to be pretty much identical to 50Hz PAL that UK Beebs notionally generate. (https://en.wikipedia.org/wiki/576i.
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noggin
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Re: Beeb FPGA

Postby noggin » Fri Sep 15, 2017 10:07 pm

From memory, 576i25 was originally not going to be catered for in the HDMI spec (which is very closely linked to DVI) as the pixel clock was too low. Instead the aim was for 'SD" devices to run at 576p50 instead (indeed Sky HD boxes in AUTO mode output 576p not 576i when tuned to SD broadcasts).

However 576i25 was added to the HDMI spec, and they got it to a high enough pixel clock by doubling the number of pixels in each line - effectively going from 720 active samples per line to 1440 - by repeating every sample twice...

50Hz support on PC monitors designed purely for PCs is quite rare, as the VGA spec never included 50Hz support as standard, and DVI was effectively derived from VGA resolutions in part. As a result lots (but not all) PC monitors with HDMI (and DVI/VGA) only support higher vertical refresh rates (and often monitors don't support low line rates either) And then you have 16-235 vs 0-255 levelspace to worry about too. And RGB vs YCbCr...

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Re: Beeb FPGA

Postby vanfanel » Tue Sep 26, 2017 6:59 pm

hoglet wrote:sn76489 model


Whoaaaa!! =D> =D> =D>
Can we have a ZX-UNO binary with this updated sn76489 model, please?? [-o<

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Re: Beeb FPGA

Postby hoglet » Tue Sep 26, 2017 7:18 pm

vanfanel wrote:Can we have a ZX-UNO binary with this updated sn76489 model, please?? [-o<

You'll need to talk to the ZX-UNO people about that...

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bakoulis
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Re: Beeb FPGA

Postby bakoulis » Tue Sep 26, 2017 10:14 pm

hoglet wrote:
vanfanel wrote:Can we have a ZX-UNO binary with this updated sn76489 model, please?? [-o<

You'll need to talk to the ZX-UNO people about that...

Can we ask you at least a new updated hoglet/b-em with the latest changes of the stardot/b-em and the VideoNuLA support from https://github.com/kieranhj/b-em/tree/feature-nula ?
:D [-o<
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Re: Beeb FPGA

Postby fordp » Wed Sep 27, 2017 7:19 am

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Re: Beeb FPGA

Postby noggin » Sun Oct 08, 2017 9:27 am

fordp wrote:Strange that as all proper HDMI monitors must support 576p and 576i. I am not sure if the pixels on the beeb can fit on a 576i mode with 1:1 pixels however?


Sadly not the case - it's only European HDTVs that mandate HDMI 50Hz support - as part of the 'HD Ready' and 'HD 1080p' licensing (was EICTA now Digital Europe) scheme.

There's no guarantee that HDMI PC monitors that don't carry the European HD Ready or similar logo will support 50Hz HDMI. (Lots of big name TVs sold in the US also don't support 50Hz refresh rates either - including Sony, Panasonic etc. )

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Re: Beeb FPGA

Postby fordp » Tue Oct 10, 2017 7:11 am

noggin wrote:
fordp wrote:Strange that as all proper HDMI monitors must support 576p and 576i. I am not sure if the pixels on the beeb can fit on a 576i mode with 1:1 pixels however?


Sadly not the case - it's only European HDTVs that mandate HDMI 50Hz support - as part of the 'HD Ready' and 'HD 1080p' licensing (was EICTA now Digital Europe) scheme.

There's no guarantee that HDMI PC monitors that don't carry the European HD Ready or similar logo will support 50Hz HDMI. (Lots of big name TVs sold in the US also don't support 50Hz refresh rates either - including Sony, Panasonic etc. )


It is very easy to get European HD Ready TVs round here ;)
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Re: Beeb FPGA

Postby noggin » Tue Oct 10, 2017 12:29 pm

fordp wrote:
noggin wrote:
fordp wrote:Strange that as all proper HDMI monitors must support 576p and 576i. I am not sure if the pixels on the beeb can fit on a 576i mode with 1:1 pixels however?


Sadly not the case - it's only European HDTVs that mandate HDMI 50Hz support - as part of the 'HD Ready' and 'HD 1080p' licensing (was EICTA now Digital Europe) scheme.

There's no guarantee that HDMI PC monitors that don't carry the European HD Ready or similar logo will support 50Hz HDMI. (Lots of big name TVs sold in the US also don't support 50Hz refresh rates either - including Sony, Panasonic etc. )


It is very easy to get European HD Ready TVs round here ;)


Yep! TVs easy, it’s PC monitors that are hit and miss.

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Re: Beeb FPGA

Postby noggin » Tue Oct 10, 2017 12:35 pm

fordp wrote:
noggin wrote:
fordp wrote:Strange that as all proper HDMI monitors must support 576p and 576i. I am not sure if the pixels on the beeb can fit on a 576i mode with 1:1 pixels however?


Sadly not the case - it's only European HDTVs that mandate HDMI 50Hz support - as part of the 'HD Ready' and 'HD 1080p' licensing (was EICTA now Digital Europe) scheme.

There's no guarantee that HDMI PC monitors that don't carry the European HD Ready or similar logo will support 50Hz HDMI. (Lots of big name TVs sold in the US also don't support 50Hz refresh rates either - including Sony, Panasonic etc. )


It is very easy to get European HD Ready TVs round here ;)


Yep! 50Hz TVs easy, it’s 50Hz HDMI PC monitors that are hit and miss :/

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hoglet
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Re: Beeb FPGA

Postby hoglet » Tue Oct 10, 2017 12:37 pm

noggin wrote:hoglet - I also may have a DE1 available to play with. I'm starting from zero experience with FPGAs (I last worked in this arena writing very simple logic with PLAs and PALs c.1992, compiling the logic code on a VAX and writing it on a VT220-clone...) - is there a good 'How to' for installing BeebFPGA on a DE1? (Apols - this should probably be in the BeebFPGA thread)

It is now!

At a high level, there are two steps involved:
1. Program the BeebFPGA ROMs image into FLASH (rom_image.bin, at address 0, using the Altera DE1 Control Panel App, windows only, erase first)
2. Download the BeebFPGA bitstream to FPGA RAM (bbc_micro_de1.sof) using the Altera Programmer software

(I prefer not to program the bitstream into Serial EEPROM, but that is also possible, use the .pof file instead of the .sof file)

These files can be found here:
https://github.com/hoglet67/BeebFpga/tr ... ra/release

There are two version of the BeebFPGA bitstream:
- bbc_micro_de1 includes the Ice T65 debugger
- bbc_micro_de1_sid_mk5 excludes the Ice T65 debugger, but includes the SID and Music 5000 (and maybe also the 6502 Co Pro)

You can fiddle with the various options here:
https://github.com/hoglet67/BeebFpga/bl ... 1.vhd#L241
and recompile the bitstream

Sorry that's a bit sketchy, it's a while since I have done this and I'd need to work through it again myself.

Dave

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Re: Beeb FPGA

Postby noggin » Tue Oct 10, 2017 1:10 pm

hoglet wrote:2. Download the BeebFPGA bitstream to FPGA RAM (bbc_micro_de1.sof) using the Altera Programmer software
Dave


Thanks Dave

Is the Altera Programmer Software called Quartus II - or is there another utility? I’ve got the Control Panel software from a download from the Terasic site.

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Re: Beeb FPGA

Postby hoglet » Tue Oct 10, 2017 3:27 pm

noggin wrote:Is the Altera Programmer Software called Quartus II - or is there another utility? I’ve got the Control Panel software from a download from the Terasic site.

Are you on Windows?

On my system the programmes can be invoked as a standalone application, called "Quartus II 13.0sp1 Programmer"

It's also available as a menu item within the main "Quartus II 13.0sp1" application.

Dave

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Re: Beeb FPGA

Postby noggin » Tue Oct 10, 2017 8:49 pm

Thanks for that info Dave - will be running Windows.

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Re: Beeb FPGA

Postby hoglet » Wed Oct 11, 2017 6:36 am

noggin wrote:Thanks for that info Dave - will be running Windows.

As far as I understand, Quartus II version 13.0 SP1 is the latest version of Quartus that includes synthesis support for the old Cyclone II FPGA on the DE1.

So make sure you download that, rather than the latest version.

Dave

vanfanel
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Re: Beeb FPGA

Postby vanfanel » Sun Oct 29, 2017 6:54 pm

@hoglet: I have found that "URIDUM" is having problems: it sounds very wrong and graphics get corrupted as soon as you start to play. Is it supposed to be compatible?

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hoglet
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Re: Beeb FPGA

Postby hoglet » Sun Oct 29, 2017 6:57 pm

vanfanel wrote:@hoglet: I have found that "URIDUM" is having problems: it sounds very wrong and graphics get corrupted as soon as you start to play. Is it supposed to be compatible?

I have no idea what "URIDUM" is, and searching the forum doesn't get any hits.

Can you provide a .ssd to test with?

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Re: Beeb FPGA

Postby BigEd » Sun Oct 29, 2017 6:58 pm

(surely Uridium http://bbcmicro.co.uk/game.php?id=557 - which interestingly enough fails for me.)

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hoglet
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Re: Beeb FPGA

Postby hoglet » Sun Oct 29, 2017 7:02 pm

I've tried the .ssd in BeebEm and it works. It's a sideways scroller, so it's possibly it's showing a up a bug in the 6845 model.

I'll do some testing on the FPGAs later.

Dave

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hoglet
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Re: Beeb FPGA

Postby hoglet » Sun Oct 29, 2017 7:25 pm

vanfanel wrote:@hoglet: I have found that "URIDUM" is having problems: it sounds very wrong and graphics get corrupted as soon as you start to play. Is it supposed to be compatible?

Can you post a screen shot showing the corruption?

I've given it a quick try on BeebFPGA and Ice40Beeb, and it's not obviously broken:
IMG_1129.JPG

What hardware are you running BeebFPGA on?

Dave

vanfanel
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Re: Beeb FPGA

Postby vanfanel » Mon Oct 30, 2017 10:43 am

Hi, Hoglet.
This is what's happening just after I redefine the keys:

https://www.dropbox.com/s/va5ygfhk7zrdk ... 0.jpg?dl=0

And this is what happens after I chose joystick as control method and let the demo run (as you see, there's an advancing row of corrupt pixels):

https://www.dropbox.com/s/w8bmgw3055fi9 ... 1.jpg?dl=0
https://www.dropbox.com/s/e595vtctodr4d ... 6.jpg?dl=0
https://www.dropbox.com/s/jzeiqkxbgiwfn ... 2.jpg?dl=0

I am on the ZX-UNO platform. If you don't have one, I can donate one to you, i'd say it's the most popular FPGA platform here in Spain.


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