Beeb FPGA

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sPhilMainwaring
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Re: Beeb FPGA

Postby sPhilMainwaring » Sat Feb 06, 2016 10:07 am

... not only are there 2 divisors but both suggestions are 4 x faster:

4 x 4 = 16
16 x 4 = 64

... then there's *TAPE and * TAPE3 for 1,200 and 300 baud (300 x 4 = 1,200)

Coincidence? or "taps" in the circuitry via the serula?

Edit: One of JG's OS disassemblies may give the poke address for the serula for triggering the 300 -> 1200 to confirm a relationship?


Here's one of my "edits" from 2012 ... not sure how similar to JG's it is ... it may, or may not, map to the circuit diagram a bit :p

extracts:

Code: Select all


\\ ***************** Control cassette system ****************************

FB50   LDA #&05   \\ Set &FE10 to 5
FB52   STA &FE10   \\ Setting a transmit baud rate of 300,motor off



Code: Select all


FB5C   LDA #&85   \\ Turn motor on and keep baud rate at 300 recieve
FB5E   STA &FE10   \\ 19200 transmit
FB61   LDA #&D0   \\ A=&D0
FB63   ORA &C6
FB65   STA &FE08   \\ Set up ACIA control register



Code: Select all


\\ **********************************************************************
\\ *                           *
\\ *   Claim serial system for cassette etc.            *
\\ *                           *
\\ **********************************************************************

FB27   LDA &E3      \\ Get cassette filing system options byte
         \\ High nybble used for LOAD & SAVE operations
         \\ Low nybble used for sequential access

         \\ 0000   Ignore errors      No messages
         \\ 0001   Abort if error      No messages
         \\ 0010   Retry after error   No messages
         \\ 1000   Ignore error      Short messages
         \\ 1001   Abort if error      Short messages
         \\ 1010   Retry after error   Short messages
         \\ 1100   Ignore error      Long messages
         \\ 1101   Abort if error      Long messages
         \\ 1110   Retry after error   Long messages

FB29   AND #&F0   \\ Clear low nybble
FB2B   STA &BB      \\ As current OPTions
FB2D   LDA #&06   \\ Set current interblock gap
FB2F   STA &C7      \\ To 6
FB31   CLI      \\ Allow interrupts
FB32   PHP      \\ Save flags on stack
FB33   SEI      \\ Prevent interrupts
FB34   BIT &024F   \\ Check if RS423 is busy
FB37   BPL &FB14   \\ If not FB14
FB39   LDA &EA      \\ See if RS423 has timed out
FB3B   BMI &FB14   \\ If not FB14
FB3D   LDA #&01   \\ else load RS423 timeout counter with
FB3F   STA &EA      \\ 1 to indicate that cassette has 6850
FB41   JSR &FB46   \\ Reset ACIA with &FE80=3
FB44   PLP      \\ Get back flags
FB45   RTS      \\ Return

FB46   LDA #&03   \\ A=3
FB48   BNE &FB65   \\ and exit after resetting ACIA

\\ ********************** Set ACIA control register *********************

FB4A   LDA #&30   \\ Set current ACIA control register
FB4C   STA &CA      \\ To &30
FB4E   BNE &FB63   \\ and goto FB63
         \\ If bit 7=0 motor off 1=motor on

\\ ***************** Control cassette system ****************************

FB50   LDA #&05   \\ Set &FE10 to 5
FB52   STA &FE10   \\ Setting a transmit baud rate of 300,motor off
FB55   LDX #&FF
FB57   DEX      \\ Delay loop
FB58   BNE &FB57
FB5A   STX &CA      \\ &CA=0
FB5C   LDA #&85   \\ Turn motor on and keep baud rate at 300 recieve
FB5E   STA &FE10   \\ 19200 transmit
FB61   LDA #&D0   \\ A=&D0
FB63   ORA &C6
FB65   STA &FE08   \\ Set up ACIA control register
FB68   RTS      \\ Return and return
FB69   LDX &03C6   \\ Block number
FB6C   LDY &03C7   \\ Block number hi
FB6F   INX      \\ X=X+1
FB70   STX &B4      \\ Current block no. lo
FB72   BNE &FB75
FB74   INY      \\ Y=Y+1
FB75   STY &B5      \\ Current block no. hi
FB77   RTS      \\ Return
FB78   LDY #&00
FB7A   STY &C0      \\ Filing system buffer flag

\\ ***************** Set (zero) checksum bytes **************************

FB7C   STY &BE      \\ CRC workspace
FB7E   STY &BF      \\ CRC workspace
FB80   RTS      \\ Return

\\ *********** Copy sought filename routine *****************************

FB81   LDY #&FF   \\ Y=&FF
FB83   INY      \\ Y=Y+1
FB84   INX      \\ X=X+1
FB85   LDA &0300,X
FB88   STA &03D2,Y   \\ Sought filename
FB8B   BNE &FB83   \\ Until end of filename (0)
FB8D   RTS      \\ Return

FB8E   LDY #&00   \\ Y=0

\\ ********************** Switch Motor on *******************************

FB90   CLI      \\ Allow IRQ interrupts
FB91   LDX #&01   \\ X=1
FB93   STY &C3      \\ Store Y as current file handle

\\ ********************* Control motor **********************************

FB95   LDA #&89   \\ Do osbyte 137
FB97   LDY &C3      \\ Get back file handle (preserved thru osbyte)
FB99   JMP OSBYTE   \\ Turn on motor


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sPhilMainwaring
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Re: Beeb FPGA

Postby sPhilMainwaring » Sat Feb 06, 2016 10:30 am

More 6850 "settings"

Code: Select all


\\ **********************************************************************
\\ *                           *
\\ *   OSBYTE 08/07   Set serial baud rates            *
\\ *                           *
\\ **********************************************************************

\\ On entry X=baud rate
\\ A=8 transmit
\\ A=7 receive

E68B   EOR #&3F   \\ Converts ASCII 8 to 7 binary and ASCII 7 to 8 binary
E68D   STA &FA      \\ Store result
E68F   LDY &0282   \\ Get serial ULA control register setting
E692   CPX #&09   \\ Is it 9 or more?
E694   BCS &E6AD   \\ If so exit
E696   AND &E9AD,X   \\ and with byte from look up table
E699   STA &FB      \\ Store it
E69B   TYA      \\ Put Y in A
E69C   ORA &FA      \\ and or with Accumulator
E69E   EOR &FA      \\ Zero the three bits set true
E6A0   ORA &FB      \\ Set up data read from look up table + bit 6
E6A2   ORA #&40
E6A4   EOR &025D   \\ Write cassette/RS423 flag

E6A7   STA &0282   \\ Store serial ULA flag
E6AA   STA &FE10   \\ and write to control register
E6AD   TYA      \\ Put Y in A to save old contents
E6AE   TAX      \\ Write new setting to X
E6AF   RTS      \\ and return

\\ ******* Serial baud rate look up table *******************************

E9AD   EQUB &64   \\ %01100100      75
E9AE   EQUB &7F   \\ %01111111     150
E9AF   EQUB &5B   \\ %01011011     300
E9B0   EQUB &6D   \\ %01101101    1200
E9B1   EQUB &C9   \\ %11001001    2400
E9B2   EQUB &F6   \\ %11110110    4800
E9B3   EQUB &D2   \\ %11010010    9600
E9B4   EQUB &E4   \\ %11100100   19200
E9B5   EQUB &40   \\ %01000000

...

F157   STX &C6      \\ Set current baud rate X=5 300 baud X=6 1200 baud

...

F196   LDA &C6      \\ else get current baud rate and zero bit 2
F198   AND #&FB   \\ C6=5 becomes 1, 6 becomes 2
F19A   ORA &0247   \\ If cassette selected A=0 else A=2
F19D   ASL      \\ Multiply by 2
F19E   ORA &0247   \\ or it again
F1A1   LSR      \\ Divide by 2
F1A2   RTS      \\ Return cassette =0



Code: Select all

\\ ************** SHEILA MOS memory-mapped I/O **************************

\\               DEVICE      WRITE         READ
FE08         \\ FE08:   6850 ACIA   Control Register   Status Register
FE09         \\ FE09:   6850 ACIA   Transmit Data      Recieve Data
FE10         \\ FE10:   SERIAL ULA   Control Register



http://www.classiccmp.org/dunfield/r/6850.pdf

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fordp
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Re: Beeb FPGA

Postby fordp » Sat Feb 06, 2016 11:34 am

Thanks Phil, that will help with the reverse engineering.

Looks like 0xFE10 is where all the SerialProc work is done.

The MSB seems to control the Reed Relay for the motor and the lower bits are used for the baud rate. I cannot see how the multiplexing between the Serial Port and Tape system is done from that yet but I sure we can find it.

I have a busy weekend doing Family things but I will get on to it when I can.

Cheers.
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hoglet
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Re: Beeb FPGA

Postby hoglet » Sat Feb 06, 2016 12:16 pm

This is what the advanced user guide has to say about the baud rate generation:
serialula.PNG

If the 6850 intended to be run with at 64x divider:
- 75 baud means it needs at 4,800 Hz clock
- 19,200 baud means it needs a 1,228,800 Hz clock

According to the BBC Micro Service Manual:
IC42 divides the 16 MHz clock signal by 13 (1.23 MHz) and this signal is divided further (by 1024) within the serial processor to produce the 1200 Hz cassette signal.

http://chrisacorns.computinghistory.org ... 5_Sec1.pdf
This actually gives you 1201.9Hz tone for the cassette, and a 1,230,769 Hz clock for serial baud rate generation.

So I guess that's all consistent, and the error is 0.16%.

These must be the Serial ULA dividers:

Code: Select all

Baud   Serial ULA Divider
   75 128
  150  64
  300  32
 1200  16
 2400   8
 4800   4
 9600   2
19200   1


The links S28 and S29 allow the IC42 divider value to be changed, by varying the pre-load value:

Code: Select all

DCBA
0111 / 9 - 75 baud becomes close to 110 baud (actually 108.3 baud)
0100 /12 1200 baud becomes 1300 baud.
0011 /13 - the default
0000 /16 - not sure this is mean to be used.

110 baud used by old teletype machines (I expect Mark has several of these!).
1300 baud was used by some old FSK modems I think, and maybe also the Spectrum?

Dave

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hoglet
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Re: Beeb FPGA

Postby hoglet » Sat Feb 06, 2016 1:48 pm

Here's a useful block diagram of the Serial ULA from the Service Manual:
http://chrisacorns.computinghistory.org ... 5_Sec1.pdf
serialula.PNG

3.5 Cassette + RS423 + serial processor
For both the cassette and RS423 interfaces, a 6850 asynchronous
communications interface adaptor (ACIA) (IC4) is used to buffer and
serialise or deserialise the data. The serial processor (IC7),
specifically designed for the BBC Microcomputer, contains two
programmable baud rate generators, a cassette data/clock separator,
switching to select either RS423 or cassette operations and also a
circuit to synthesise a sinewave to be fed out to the cassette
recorder. IC42 divides the 16 MHz clock signal by 13 (1.23 MHz) and
this signal is divided further (by 1024) within the serial processor to
produce the 1200 Hz cassette signal. Automatic motor control of an
audio cassette recorder is achieved by using a small relay driven by a
transistor (Q3) from the serial processor. The signal coming from the
cassette recorder is buffered, filtered and shaped by a three stage
amplifier (IC35). The RS423 data in and data out signals and the
request to send output (RTS) and clear to send input (CTS) signals are
interfaced by ICs 74 and 75 which translate between TTL and standard
RS423/232 signal levels (+5V and -5V). The control register, which is
memory-mapped at &FE10, specifies the frequencies for the transmit
clock (bits 0-2) and the receive clock (bits 3-5) used by the 6850 (
IC4). The switching between the cassette and RS423 inputs and outputs
19
is also determined by the control register (bit 6), and so is the motor
control (bit7). R75 and C28 provide the necessary timing elements for
delay between receiving the high tone run-in signal and asserting the
data carrier detect signal to the ACIA. The value of resistor needed is
affected by the output impedance of that pin on the serial. processor
which has been subject to a certain amount of variation. Thus the value
of R75 has changed through the evolution of the circuit.

The only non-trivial bits are the high tone detect and the clock/data separator.

Dave

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Re: Beeb FPGA

Postby sPhilMainwaring » Sat Feb 06, 2016 1:52 pm

The values in the User Guide don't seem to relate in any obvious way with the baud rate look up table at &E9AD which I suspect are the actual values that are poked to the memory mapped addresses in either the SerULA or ACIA direct (or maybe even a combination of the two and / or some discrete logic gates)

I wrote a terminal emulation program for the Beeb back in the day that, naughtily, poked the ACIA control and peeked the ACIA status registers directly ... if this doesn't match the bit patterns of the status and control register there may be similar discrete / SerULA "jiggerry pokery" going on in that the signals might double in function to turn on/off the tape tone generators, etc.

Would examining the circuit diagram and throwing various poke values at the locations on a real Beeb hooked up to some investigation equipment might help if stuck on certain trackings ?

I've put my edit of OS1.2 here in case anyone needs it

http://phils-place.co.uk/bbc/BBC_OS_1_2_edit_6.asm

Searching for TAPE, SERIAL, BAUD, ACIA, 300 in the above file throws up interesting areas of the ROM :-)

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Re: Beeb FPGA

Postby fordp » Sat Feb 06, 2016 2:15 pm

Well done everyone.

Dave feel free to merge my changes and implement the tape/rs423. I will then be able to clone your work changing the second MC8650 clock to 500khz and have a working MIDI interface ;)
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Re: Beeb FPGA

Postby hoglet » Sat Feb 06, 2016 2:17 pm

sPhilMainwaring wrote:The values in the User Guide don't seem to relate in any obvious way with the baud rate look up table at &E9AD which I suspect are the actual values that are poked to the memory mapped addresses in either the SerULA or ACIA direct (or maybe even a combination of the two and / or some discrete logic gates)

The comments in your table are offset by one, because X have values 1 (75 baud) to 8 (19200 baud), not 0 to 7.

If you move the comments, it makes a bit more sense:

Code: Select all

\\ ******* Serial baud rate look up table *******************************
E9AD   EQUB &64   \\ %0 1 100 100
E9AE   EQUB &7F   \\ %0 1 111 111      75
E9AF   EQUB &5B   \\ %0 1 011 011     150
E9B0   EQUB &6D   \\ %0 1 101 101     300
E9B1   EQUB &C9   \\ %1 1 001 001    1200
E9B2   EQUB &F6   \\ %1 1 110 110    2400
E9B3   EQUB &D2   \\ %1 1 010 010    4800
E9B4   EQUB &E4   \\ %1 1 100 100    9600
E9B5   EQUB &40   \\ %0 1 000 000   19200

These do then match up with the values from the Advanced User Guide.

The binary numbers (e.g. bits 2..0) need to be read backwards.

There's some more good info here:
http://beebwiki.mdfs.net/Serial_ULA

Dave
Last edited by hoglet on Sat Feb 06, 2016 2:25 pm, edited 1 time in total.

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Re: Beeb FPGA

Postby sPhilMainwaring » Sat Feb 06, 2016 2:25 pm

hoglet wrote:
The comments in your table are offset by one, because X have values 1 (75 baud) to 8 (19200 baud), not 0 to 7.

If you move the comments, it makes a bit more sense:



Well spotted Dave ... I did have a quick scan but my binary eye must be out of practice :)

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Re: Beeb FPGA

Postby fordp » Sat Feb 06, 2016 5:37 pm

I never realised the Beeb was capable of 38400 and 76800 baud. We could implement the 110 baud by adding an extra register. We only need one bit however to enable it. 110 was important for teletypes.
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Re: Beeb FPGA

Postby fordp » Sat Feb 06, 2016 5:39 pm

hoglet wrote:The only non-trivial bits are the high tone detect and the clock/data separator.

Dave

It is all non trivial for me with my HDL skills ;)
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Re: Beeb FPGA

Postby sweh » Sun Feb 07, 2016 3:19 pm

sPhilMainwaring wrote:Edit: One of JG's OS disassemblies may give the poke address for the serula for triggering the 300 -> 1200 to confirm a relationship?

IIRC, JGH's HostFS ( http://mdfs.net/Software/Tube/Serial/ ) resets the divider to be 4 times faster, so if you configure for 4800 baud (*FX7,6 *FX8,6) then it really talks at 19,200.
Rgds
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Re: Beeb FPGA

Postby fordp » Sun Feb 07, 2016 7:50 pm

I have done my best to add a Midi port and I am making headway.

Code: Select all

--------------------------------------------------------
-- Optional Midi Interface
--------------------------------------------------------
      Optional_MidiInterface: if IncludeMidi generate
     
         Inst_MC6850: entity work.WF6850IP_TOP
            port map (
               CLK      => clock_32,
               RESETn   => reset_n,
               CS2n     => '0',
               CS1      => '1',
               CS0      => midi_enable,
               E        => mhz1_clken,
               RWn      => cpu_r_nw,
               RS       => cpu_a(0),
               
               --  TO DO DATA
               
               TXCLK    => mhz2_clken,
               RXCLK    => mhz2_clken,
               RXDATA   => midi_in,
               CTSn     => '0',
               DCDn     => '0',
               IRQn     => midi_irq_n,               
               TXDATA   => midi_out
               
               -- RTS Unnconected
             );
             
      end generate;


The issues I have at the moment is that the 6850 HDL I have has the data bus declared as:

Code: Select all

        DATA              : inout std_logic_vector(7 downto 0);


I am not sure how to hook that in to Dave's code.

I will do some reading ...
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Re: Beeb FPGA

Postby hoglet » Sun Feb 07, 2016 8:02 pm

Generally it's best to avoid INOUT ports internally in an FPGA. They imply the internal drivers should be tristated, which is not support by FPGAs. The XIlinx/Altera FPGA tools try to convert these to logic, but I've seen some seen results. Best to use separate Din and Dout ports if possible.

Dave

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Re: Beeb FPGA

Postby fordp » Sun Feb 07, 2016 8:40 pm

This was my fault.

There are two separate tops defined one for internal SOC use and one stand alone use. I will fix it later!
Last edited by fordp on Mon Feb 08, 2016 8:24 am, edited 1 time in total.
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Re: Beeb FPGA

Postby fordp » Sun Feb 07, 2016 9:24 pm

I have switched to the correct 6850 top now and hooked up the Data Bus.

I will install my new logic analyser and test MIDI sometime next week. I have checked my changes in to my forked branch.

If I get the Midi working then the RS423 should be not too bad after that. It could be done in two stages i.e. add RS423 only support first and then add the Tape support after that.
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Re: Beeb FPGA

Postby fordp » Mon Feb 08, 2016 8:08 pm

I have tried a bit of testing and if I:

Code: Select all

PRINT ?&FCF0


Then it returns zero which is different to elsewhere in the page so maybe it is reading the Status register ?
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Re: Beeb FPGA

Postby hoglet » Mon Feb 08, 2016 8:31 pm

fordp wrote:I have tried a bit of testing and if I:

Code: Select all

PRINT ?&FCF0


Then it returns zero which is different to elsewhere in the page so maybe it is reading the Status register ?

Looks promising! I'll give it a go tomorrow.

Why not drive '1's into CTS and DCD and see if bits 2 and 3 of the status register change?

Dave

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Re: Beeb FPGA

Postby fordp » Mon Feb 08, 2016 8:38 pm

Well it helps if you put your logic probes on the correct pins ;)

midi01.jpg


I am sending some data 0x01 in this case !

I am getting some bytes sent twice and basic is very slow sending data but it looks promising :D

Great if you can look over what I have done Dave.

I have done most of the MIDI. I am using a 2MHz baud clock which will work with divide by 64. A 500khz baud clock (x16) seems more common in real interfaces however so may have better compatibility with sequencing software. I should probably more tightly decode the address lines so the UART only takes 2 addresses. I just did it the simplest way to start with.

Go easy on me this is my first HDL for over 5 years. I was amazed I could actually make it build.
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Re: Beeb FPGA

Postby hoglet » Fri Feb 12, 2016 11:42 am

It would be nice to have a way of emulating an AMX compatible mouse on Beeb FPGA. We would have to add a second user port (or memory mapped SPI port), and have MMFS use that instead of the normal user port, but that's very easy to do.

I've looked as how people are doing PS/2 to Quadrature conversion, and most implementations used a PIC or an AVR. I haven't seen a pure VHDL solution that gives you back the quadrature signals. Writing one is probably not that hard, but I'm not feeling very motivated to dive into this at the moment.

The other challenge would be sending the command to put the mouse into three-button mode, as I think the default on power up is two-button mode. So the PS/2 interface (and external level shifters) would have to be bidirectional and support host-to-mouse commands. These exist though.

I'm wondering if there is an easier option....

Ford, do you have any quadrature mice (e.g. an old amiga or atari mouse). These could pretty much be directly connected (with 3K3/1K8 resistive dividers to do the level shifting). I think I have a couple lying around. But they are only two-button.

Is it important to have the third (middle) button present and working? I would guess it is for the AMX Software, but less so for DOS Plus/Gem.

The final option might be to use one of the eBay mice that people have been hacking for quadrature conversion. Daniel put up some instructions here:
http://www.stardot.org.uk/forums/viewto ... f=3&t=6869

The original PS/2 mice are no longer available, but the USB version is apparently also convertible:
http://www.stardot.org.uk/forums/viewto ... 69#p130699

And looking at the data sheet, it's a 3.3V device, so no level shifting would be needed.

I've just bought a couple to play with (at £1.99 each):
http://www.ebay.co.uk/itm/E-Cheetah-opt ... 1279315310

Dave

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Re: Beeb FPGA

Postby fordp » Fri Feb 12, 2016 12:06 pm

I have no quadrature ball mice apart from my real AMX mouse. They all barely worked so I threw them out.

I have just ordered a couple of mice from your Ebay link.

AMX PageMaker here we come ;)
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Re: Beeb FPGA

Postby fordp » Tue Feb 16, 2016 11:04 am

Hi Dave,

The following is troubling me today:

You state above that you could not find any PS/2 to Quadrature HDL. Does this IP not exist in both Suska (Atari ST) and Minimig (Amiga) platforms at least?

Cheers.
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Re: Beeb FPGA

Postby hoglet » Tue Feb 16, 2016 11:12 am

fordp wrote:You state above that you could not find any PS/2 to Quadrature HDL. Does this IP not exist in both Suska (Atari ST) and Minimig (Amiga) platforms at least?

I could not find it in Mimimig. I found some mouse emulation VHDL code from the keyboard, but not from a PS/2 mouse. But I'm not very familiar with either of these projects, so I possibly just missed it.

Dave

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Re: Beeb FPGA

Postby 1024MAK » Tue Feb 16, 2016 11:40 am

In real Atari STFMs and STEs, it's the keyboard micro-controller that processes the mouse signals (they get converted to a serial data packet), so the main board never sees a quadrature mouse signal.

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Re: Beeb FPGA

Postby fordp » Tue Feb 16, 2016 12:37 pm

Thanks for that Mark but are the physical mice Quadrature or some some other system?
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Re: Beeb FPGA

Postby hoglet » Tue Feb 16, 2016 12:39 pm

hoglet wrote:
fordp wrote:You state above that you could not find any PS/2 to Quadrature HDL. Does this IP not exist in both Suska (Atari ST) and Minimig (Amiga) platforms at least?

I could not find it in Mimimig. I found some mouse emulation VHDL code from the keyboard, but not from a PS/2 mouse. But I'm not very familiar with either of these projects, so I possibly just missed it.

Just to follow up on this.

Suska includes an external Atmel ATmega16 AVR microcontroller to handle the PS/2 keyboard and mouse. The C code for this is here:
http://download.experiment-s.de/Suska/2 ... 319.tar.gz
So this is not very useful to us.

The original Minimig only supported a PS/2 Keyboard with mouse emulation using the numeric keypad.
https://github.com/mist-devel/mist-boar ... Keyboard.v

But it seems in 2014 proper PS/2 mouse support was added to a module called UserIO:
https://github.com/rkrajnc/minimig-de1/ ... io.v#L1149
This doesn't output quadrature signals, but seems to provide a memory mapped version of the absolute mouse position. I don't know enough about Minimig to understand how this is then used.

There actually is a similar module in the Atom GODIL Video adapter that works well:
https://github.com/hoglet67/AtomGodilVi ... roller.vhd
So the difficult bidirectional PS/2 protocol stuff does exist in a form I'm familiar with.

What's missing is a state machine to re-generate quadrature signals from the positional outputs of this. This would load a counter with the value representing the change in mouse position, and then count down at a slow ish clock rate. At each count position the quadrature outputs would toggle. Maybe I'll have a go at this after all.

Dave

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Re: Beeb FPGA

Postby hoglet » Tue Feb 16, 2016 12:44 pm

Ford,

Do you still have this "fordp" mod in place on your DE1?
http://zet.aluzina.org/forums/viewtopic ... 1801#p1801

If so I might do the same....

Dave

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Re: Beeb FPGA

Postby fordp » Tue Feb 16, 2016 12:46 pm

hoglet wrote:
hoglet wrote:
fordp wrote:You state above that you could not find any PS/2 to Quadrature HDL. Does this IP not exist in both Suska (Atari ST) and Minimig (Amiga) platforms at least?

I could not find it in Mimimig. I found some mouse emulation VHDL code from the keyboard, but not from a PS/2 mouse. But I'm not very familiar with either of these projects, so I possibly just missed it.

Just to follow up on this.

..Snip
Dave


Thanks Dave,

If we can use PS/2 as is it will make Beeb FPGA more accessible. 8 bit Acorn for All ;)

I have not removed the modification. It says in that post that I modified it, this is not strictly true, the same guy who fixed my DE1 added that modification. My eyesight makes soldering hard these days!

I just noticed the date on that post. I have been doing this hobby now for over 7 years, ho hum!

I have a splitter cable somewhere!
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Re: Beeb FPGA

Postby fordp » Tue Feb 16, 2016 12:53 pm

FordP (Simon Ellwood)
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Re: Beeb FPGA

Postby hoglet » Tue Feb 16, 2016 12:57 pm

fordp wrote:http://www.ebay.co.uk/itm/Belkin-PS2-PS-2-Keyboard-mouse-splitter-cable-30cm-Belkin-Pro-Series-/261307623062?hash=item3cd725e696:g:R~4AAOSwxN5Waykx

Thanks. I think I might actually have a splitter already in one of my many useful cable boxes.

Dave


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