Beeb FPGA

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hoglet
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Re: Beeb FPGA

Postby hoglet » Wed Nov 25, 2015 2:19 pm

Hi Guys,

Some updates this morning, fixing some recently reported issues.

Here the change log:
- Fixed 6845 bug - regs 12/13 now readable as per hd6845sp datasheet
- Fixed bugs in the audio mixer causing overflow
- Boosted level of Music 5000 - need to be watch out for overflow with lots of voices
- Updated CMOS RAM to initialize screen mode and boot settings from DIP switches (and set loud by default)
- Altera DE1 build - updated binaries
- MMFS 1.04 - Fixed Bad Sum error on power up autoboot

The DIP switches for mode selection and no boot/boot should work consistently between the Model B and Master modes.

For the Altera DE1 build, the binaries are up to date. However, the rom_image will need to re-programmed into the FLASH to pick up the MMFS fix.

For the Xilinx Papailio Duo build, I've not updated the binaries yet - just shout if you need me to do that.

Dave

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Re: Beeb FPGA

Postby fordp » Wed Nov 25, 2015 6:07 pm

I have just pulled the latest from Github, programmed the Flash, built the image in Quartus || and sent it to my DE1.

Flip Audio now works, thanks Dave.

I will test some other sound stuff I have.

[Edit] Everything music file I have tried now works! Yay, great job!

As you might have guessed from my previous posts music was a big thing for me on my BBC back in the day.

I need to work towards getting my BBC Midi setup working.

I will not be happy until I can hear Captain Pugwash on my replacement CZ101 (my original one from the '80s blew up long ago).

When I have got back to where I was then we can move forward to improve on the BBC Micro ;)

Cheers.

FordP
Last edited by fordp on Wed Nov 25, 2015 10:29 pm, edited 1 time in total.
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Re: Beeb FPGA

Postby fordp » Wed Nov 25, 2015 7:09 pm

Just tested BEEB SID VIII the Queen disk.

I get sound out of my speakers!

I do not have a real Sid Play so I cannot compare the quality.

I am guessing some of the voices on B Bohemian Rhapsody are quieter than a real SID.

Maybe I should get my real C64 from the loft ;)

FordP
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TheCorfiot
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Re: Beeb FPGA

Postby TheCorfiot » Wed Nov 25, 2015 10:23 pm

Cheers Dave :)

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hoglet
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Re: Beeb FPGA

Postby hoglet » Thu Nov 26, 2015 2:05 pm

Hi Guys,

I've slowly been cleaning up the Papilio Duo (Xilinx) build:
- eliminated all warnings during the implementation and bit generation phases
- added a proper set of timing constraints to the .ucf file
- got rid of all gated clocks =D> =D> =D>
- improved the timing control of the RAM WE signal (using an ODDR2 register, which is a neat trick I read about)
- increased the drive on the SRAM interface to 8mA.

All this has been pushed to git, and there is a new bitstream if anyone wants to try it:
https://github.com/hoglet67/BeebFpga/tr ... nx/release

I've just managed by built it with all feature include (i.e. SID, Music 5000 and the ICE T65 debugger). However, it's 100% full now, so I'll probably end up doing what I've done for the Altera, and split it into two builds.

The timing on the SRAM interface at 32MHz it very tight indeed, but it just about meets it, with about 2ns spare for PCB routing delays. This is "worst case" so in practice it should be fine.

There's also been a small change to MMFS (now at version 1.05) to ensure the current drive setting are reset on Ctrl-BREAK, which 1.04 didn't do. I've pushed a new ROM image for the Altera build:
https://github.com/hoglet67/BeebFpga/tr ... ra/release

Please let me know if anything seems broken.

Dave
Last edited by hoglet on Thu Nov 26, 2015 7:21 pm, edited 1 time in total.

grannyg
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Re: Beeb FPGA

Postby grannyg » Thu Nov 26, 2015 5:10 pm

A big improvement on the Papilio duo. =D> All the games I've tried work ok in BBC mode. Not tried Master mode yet.

One minor thing. The speech in Citadel, Repton 3 and Superior Speech is really quiet and a bit scratchy.

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Re: Beeb FPGA

Postby hoglet » Thu Nov 26, 2015 5:40 pm

grannyg wrote:A big improvement on the Papilio duo. =D> All the games I've tried work ok in BBC mode. Not tried Master mode yet.

One minor thing. The speech in Citadel, Repton 3 and Superior Speech is really quiet and a bit scratchy.

That doesn't really surprise me.

There's some information here about how the SN76489 can be coerced into playing back sampled sounds:
http://www.smspower.org/Development/SN76489

The trick that was used was to set the frequency register to zero, which resulted in a DC output whose level could be modulated with the 4-bit volume. Probably the VHDL I'm currently using doesn't get this behaviour right.

I'll have a quick look around, and see if anyone has done any work on this recently.

There's a nice test program that I might have a play with here:
http://bbc.nvg.org/doc/Speech.html

Dave

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Re: Beeb FPGA

Postby tricky » Thu Nov 26, 2015 6:37 pm

I think 0 on the beeb actually generates the lowest note, same as half the startup tone if memory serves. To play samples, you set the highest frequency 1 and then modulate with the volume as you say. You can make things a little louder and get slightly more levels by doing the same thing on all three channels but with slight variations in volume. This is what the sampled speech on loading AstroBlaster does.
Speaking of speech on AstroBlaster, is tms5220 on the sound todo list ;)

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Re: Beeb FPGA

Postby hoglet » Tue Dec 01, 2015 7:28 pm

Hi Guys,

The next stage of the Dave and FordP's evil master plan to conquer the universe is now complete :shock: :shock: :shock:

Beeb FPGA now includes a built-in 4MHz 65C02 Co Pro, with a full 64K of RAM. The Co Pro is using external RAM, as I found a way to interleave access between the host CPU, the 6845 and the Co Pro CPU. There's still some spare cycles, so I might be able to run the Co Pro at 8MHz if desired.

To squeeze this in I had to re-jig the FLASH memory map, so on the Altera DE1 build you'll need to re-flash the ROM image, which is now 512KB in size.

Everything is pushed to github.

On the Altera DE1 build, you need to put SW6 in the up position to enable the Co Pro.

On the Xilinx Build, you need to install DIP3 to enable the Co Pro.

If you want to "test" with Tube Elite, and are using the STH BEEB.MMB image.

Code: Select all

*DIN 45
*TUBEELT


Ford, tomorrow I'll create a new Co Pro that provides an external SPI interface.

Dave

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Re: Beeb FPGA

Postby TheCorfiot » Tue Dec 01, 2015 10:32 pm

Quick, Where's my DE1....

Dave, Will the 512k size rom file overwrite the Elk Rom file in the flash?


Cheers

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Re: Beeb FPGA

Postby hoglet » Tue Dec 01, 2015 10:35 pm

TheCorfiot wrote:Dave, Will the 512k size rom file overwrite the Elk Rom file in the flash?

No, it doesn't. 512KB goes from 0x000000 to 0x07FFFF, and the Elk ROM starts at 0x080000.

But....to re-program the Beeb ROM you need to erase the whole device, so you'll need to re-program both images.

Hope that makes sense....

Let me know if you manage to get this working. :D

Dave

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Re: Beeb FPGA

Postby TheCorfiot » Tue Dec 01, 2015 11:00 pm

Cheers buddy, thats tonights tinkering sorted ;)

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Re: Beeb FPGA

Postby TheCorfiot » Tue Dec 01, 2015 11:36 pm

Well what can I say....
Very Impressive Dave, works perfectly from 1st release.

Mate, this project is almost complete and in so little time....:)

I know this is a toughie but is surely the icing on the cake, Saveable CMOS settings, whether you can utilise a cmos.bin file on the SD card or use some bytes in the flash ram.. but it would really be the ultimate BBC Master FPGA system.

If you can get the copro to run at 8Mhz via a switch then great but 4 is better than nowt.

Amazing work, I salute you sir
:)

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Re: Beeb FPGA

Postby fordp » Tue Dec 01, 2015 11:46 pm

Wow amazing progress. This is all without using the SDRAM. I originally sent Zeus a DE1 to get his project in to the main stream. He then worked wonders and ported his project to the the DE0 which did not have any SRAM. This should mean that the 80186 Second Processor can run in the SDRAM while the Beeb makes use of the SRAM. This should perform at least as well as a Real ABC Workstation (x86 based) :D

The DE1 is a very old board these days but can do amazing stuff with three separate memories!

Cheers,

FordP
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Re: Beeb FPGA

Postby hoglet » Wed Dec 02, 2015 7:26 am

TheCorfiot wrote:I know this is a toughie but is surely the icing on the cake, Saveable CMOS settings, whether you can utilise a cmos.bin file on the SD card or use some bytes in the flash ram.. but it would really be the ultimate BBC Master FPGA system.

Hmmm, this is indeed a toughie.

Remember, this is an actual hardware implementation (i.e. registers and gates), not a software emulator. So having the "hardware" read a cmos.bin file from a FAT formatted SD card is very hard.

I think using FLASH would be possible. The S29AL032D does support sector erase as well as chip erase. I have some 6502 code for Atom FPGA that allows the flash to be re-programmed in-situ:
https://github.com/hoglet67/AtomFpga/bl ... /flash.inc
In principle this could be re-worked as a hardware state machine. But a sector erase takes a long time, during which the BeebFpga would have to be stopped.

A third option is to use some bytes at the end of the EPCS4 serial EEPROM, which can be read/written via JTAG. On the Xilinx board, these signals can be controlled from within a design. Not sure yet if the same it true for Altera.

Anyway, I'll add it to the list, but no promises....

Dave
Last edited by hoglet on Wed Dec 02, 2015 7:50 am, edited 2 times in total.

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Re: Beeb FPGA

Postby hoglet » Wed Dec 02, 2015 7:36 am

fordp wrote:Wow amazing progress. This is all without using the SDRAM. I originally sent Zeus a DE1 to get his project in to the main stream. He then worked wonders and ported his project to the the DE0 which did not have any SRAM. This should mean that the 80186 Second Processor can run in the SDRAM while the Beeb makes use of the SRAM. This should perform at least as well as a Real ABC Workstation (x86 based) :D

This would be cool.

We're already using the Zet core on the Matchbox Co Pro, and had to enhance it in a few places to get it working.

The x86 Client ROM is quite large - 16K I think - and it's not immediately obvious where that would go.

Dave

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Re: Beeb FPGA

Postby fordp » Wed Dec 02, 2015 8:03 am

TheCorfiot wrote:I know this is a toughie but is surely the icing on the cake, Saveable CMOS settings, whether you can utilise a cmos.bin file on the SD card or use some bytes in the flash ram.. but it would really be the ultimate BBC Master FPGA system.

Amazing work, I salute you sir
:)


Two ways to make this happen,
1) Write a Sideways ROM to load the settings from SD Card, this may end up loading the settings too late:
2) Modify the Second Processor ROM to load the settings from SD Card. The Second Processor could hold the main processor in Reset until the settings have been loaded.

EDIT: 2 is tricky as the CoPro is not directly connected to the SD Card hardware.

Sometimes all you need is a bit of Software ;)

FordP
Last edited by fordp on Wed Dec 02, 2015 10:35 am, edited 1 time in total.
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Re: Beeb FPGA

Postby hoglet » Wed Dec 02, 2015 9:35 am

I'd quite like the persistent configuration to be a hardware solution.
hoglet wrote:A third option is to use some bytes at the end of the EPCS4 serial EEPROM, which can be read/written via JTAG. On the Xilinx board, these signals can be controlled from within a design. Not sure yet if the same it true for Altera.

It seems that this would be possible, and there is a Altera Mega Function called ALTASMI_PARALLEL that might help.
https://www.altera.com/zh_CN/pdfs/liter ... g_asmi.pdf
However, I've searched around a bit, and I can find no examples of this being used on the DE1 board, so I might be missing something.

Dave

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Re: Beeb FPGA

Postby TheCorfiot » Wed Dec 02, 2015 10:25 am

Hi Dave
I knew the SD option was near impossible, tbh at the end of the day its not that critical because we can create a !CMOS file with configure commands which can be Exec'd straight after power on :)

Thanks for everything :D

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Re: Beeb FPGA

Postby fordp » Wed Dec 02, 2015 10:45 am

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Re: Beeb FPGA

Postby fordp » Wed Dec 09, 2015 12:19 pm

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Re: Beeb FPGA

Postby fordp » Sat Jan 09, 2016 10:30 am

Hi Dave,

I am just getting myself back on the hamster wheel after a break over Christmas. I notice you have updated MMFS, great stuff but the rom_image.bin has not been updated. Are the scripts to update the ROMs in Github, if not can you update the rom_image.bin.

I am attempting to get the Pi ARM Evaluation System running on my DE1/ RPI1 at the moment.

I will try and get my Matchbox LX9/ Pi Zero combination going next week when I can get the kit to work for my colleague who is a whizz with a soldering iron can put that together for me.

Cheers.
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Re: Beeb FPGA

Postby hoglet » Sat Jan 09, 2016 11:28 am

fordp wrote:I am just getting myself back on the hamster wheel after a break over Christmas. I notice you have updated MMFS, great stuff but the rom_image.bin has not been updated. Are the scripts to update the ROMs in Github, if not can you update the rom_image.bin.

But it's all a bit fiddly, so I've updated the release ROM image to include MMFS 1.07:
https://github.com/hoglet67/BeebFpga/tr ... ra/release

In case you (or anyone else) ever wants to do this manually:

The MMFS build script is here:
https://github.com/hoglet67/BeebFpga/bl ... s/build.sh

You then need to copy MAMMFS to roms/m128/mmfs-m.rom

The ROM Image build script is here:
https://github.com/hoglet67/BeebFpga/bl ... m_image.sh

You end up with a rom_image.bin in roms/tmp

And the scripts are for Linux.
fordp wrote:I am attempting to get the Pi ARM Evaluation System running on my DE1/ RPI1 at the moment.

Keep us posted! I haven't actually run this combination yet.

Dave

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Re: Beeb FPGA

Postby fordp » Thu Feb 04, 2016 6:50 pm

I have forked Github and I am attempting to add two new features to Beeb FPGA namely a real BBC Micro UART and a real MIDI Interface.

Those in the know will understand that both these tasks were originally done using the venerable MC6850 UART which I have carefully extracted from the LGPL Suska Atari ST project.

You can watch my laughable efforts at HDL here : https://github.com/fordp2002/BeebFpga

This could take some time ;)

This is all in done using best engineering practice of proving the HDL ahead of me trying to put it in to my own Zero CoPro project.

All I can say is do not hold your breath!

This is theory is also a cog in the works of adding real tape support to the BeebFPGA project. I have no idea if anybody is interested in that but it is possible one day assuming somebody who really knows what they are doing turns up :D
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Re: Beeb FPGA

Postby hoglet » Thu Feb 04, 2016 7:23 pm

fordp wrote:This is theory is also a cog in the works of adding real tape support to the BeebFPGA project. I have no idea if anybody is interested in that but it is possible one day assuming somebody who really knows what they are doing turns up :D

I definitely would be.

It was fun adding real tape support to ElectonFPGA. I used the Altera DE1's SPI ADC to extract the audio waveform and just send a clipped version of it into the VHDL ULA. I was pretty surprised that it worked at all. But it actually works really well, and was my main way of loading games for testing prior to MMFS existing.

I'm a bit fuzzy on exactly what goes on in the serial ULA to condition the signal so it's suitable for the 6850.

Dave

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Re: Beeb FPGA

Postby fordp » Thu Feb 04, 2016 7:40 pm

That is great news as it looks like you have the Audio side of things already sorted.

I have no idea on the details of the insides of the SerProc but it is pretty simple as far as I can see.

It switches the MC6850 between the Serial Port on the back and the Tape Interface and provides a Baud Rate generator for the MC6850.

The only puzzling thing the last time I looked was that the clock signal input looked too slow to generate a 19200 x 16 clock for the UART.

To those that know more than me please chip in now!

EDIT:
On the BBC Micro IC42 a 74LS163 generates the Clock from the 16MHz clock which goes in to pin 25 of SerProc. Jumpers S29 and S28 are also involved along with part of IC50 acting as an inverter.
Last edited by fordp on Thu Feb 04, 2016 7:49 pm, edited 1 time in total.
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Re: Beeb FPGA

Postby BigEd » Thu Feb 04, 2016 7:44 pm

The 6850 can use either a 16x or a 4x clock, according to a control bit. So for the fastest baud rates, it's necessary to configure as 4x. The OS will take care of configuring both the serial ULA and the 6850.

(IIRC)

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Re: Beeb FPGA

Postby fordp » Thu Feb 04, 2016 7:51 pm

I thought the 6850 could use a x16 or x64 clock. I have seen PICs that use a x4 Clock but that needs some weird logic to make work.

I am quitting for the night, anyone who feels like downloading my efforts and making it work while I drink tea is more than welcome ;)
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Re: Beeb FPGA

Postby BigEd » Thu Feb 04, 2016 7:57 pm

Ah, you're quite right. (But there are two divisors possible, so I got that right!)
http://www.electronics.dit.ie/staff/tsc ... a/6850.htm

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Re: Beeb FPGA

Postby sPhilMainwaring » Sat Feb 06, 2016 9:52 am

... not only are there 2 divisors but both suggestions are 4 x faster:

4 x 4 = 16
16 x 4 = 64

... then there's *TAPE and * TAPE3 for 1,200 and 300 baud (300 x 4 = 1,200)

Coincidence? or "taps" in the circuitry via the serula?

Edit: One of JG's OS disassemblies may give the poke address for the serula for triggering the 300 -> 1200 to confirm a relationship?


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