Beeb FPGA

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hoglet
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Re: Beeb FPGA

Postby hoglet » Mon Oct 30, 2017 12:44 pm

I'm not able to reproduce this myself on my Papilio Duo.

Can you upload the .ssd that you are using so we can eliminate any differences from that?

Is the ZX Uno using MMFS or Smart SPI?

Dave

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bakoulis
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Re: Beeb FPGA

Postby bakoulis » Mon Oct 30, 2017 1:41 pm

It uses Smart SPI.
2xElectron, 3xBBC B, BBC Master.
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hoglet
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Re: Beeb FPGA

Postby hoglet » Mon Oct 30, 2017 1:59 pm

bakoulis wrote:It uses Smart SPI.

I've managed to reproduce the problem on a real model B, by using Smart SPI rather than MMFS.

So it's seems to be an incompatibility with Smart SPI rather than anything to do with Beeb FPGA.

It's up to the maintainer of the Zx Uno BBC core whether they want to try using MMFS instead. It's swings and roundabouts, as there are probably some games that will work with Smart SPI but not MMFS. My preference is always MMFS, but then I'm biased as I maintain it!

Dave

vanfanel
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Re: Beeb FPGA

Postby vanfanel » Mon Oct 30, 2017 5:56 pm

@hoglet: Thanks! I don't really know how hard swiching from SPI to MMFS would be. Is it as easy as swapping the used ROM or does it also need a different SD access system implementation?

@bakoulis: If it's easy we may ask azesmbog, who did the updated port with Speech! compatibility... what do you think?

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hoglet
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Re: Beeb FPGA

Postby hoglet » Mon Oct 30, 2017 6:08 pm

vanfanel wrote:@hoglet: Thanks! I don't really know how hard swiching from SPI to MMFS would be. Is it as easy as swapping the used ROM or does it also need a different SD access system implementation?

You just need to swap the ROM image.

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Re: Beeb FPGA

Postby bakoulis » Mon Oct 30, 2017 6:29 pm

vanfanel wrote:@bakoulis: If it's easy we may ask azesmbog, who did the updated port with Speech! compatibility... what do you think?


I thing is easy job for azesmbog, but I am afraid MMFS will be more incompatible with games, as Hoglet said.
Anyway will be useful to have 2 flavors of BBC core, because ZX1 have 40 core slots!
Don't forget if you asking azesmbog to build a MMFS version, to use last build with Speech! compatibility.
:D
Will be interesting to see if Smart SPI corrupts Uridium as well on real hardware.
:?:
2xElectron, 3xBBC B, BBC Master.
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hoglet
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Re: Beeb FPGA

Postby hoglet » Mon Oct 30, 2017 6:36 pm

bakoulis wrote:Will be interesting to see if Smart SPI corrupts Uridium as well on real hardware.
:?:

It does.

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Re: Beeb FPGA

Postby hoglet » Mon Oct 30, 2017 6:41 pm

bakoulis wrote:I thing is easy job for azesmbog, but I am afraid MMFS will be more incompatible with games, as Hoglet said.

No, I didn't say it would be *more* incompatible. I said that there may be examples of games that work with SmartSPI but not MMFS. And visa versa. I know of only one example that fails with MMFS: Elixir

I don't think anyone has worked through the whole catalogue and tested each game with both file systems.

If there were space in Zx Uno, it would be best to include both and make them switchable.

Dave

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Re: Beeb FPGA

Postby bakoulis » Mon Oct 30, 2017 6:50 pm

ZX1 have space for up to 40 cores.
So, we can have every available core installed and the free space will be almost 50%.
:D
2xElectron, 3xBBC B, BBC Master.
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Re: Beeb FPGA

Postby bakoulis » Tue Oct 31, 2017 8:07 am

hoglet wrote:
vanfanel wrote:@hoglet: Thanks! I don't really know how hard swiching from SPI to MMFS would be. Is it as easy as swapping the used ROM or does it also need a different SD access system implementation?

You just need to swap the ROM image.

I just wonder, if is possible to put both SPI & MMFS on the same core and switch between roms with * commands like with romboards on real hardware?
:?:
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Re: Beeb FPGA

Postby hoglet » Tue Oct 31, 2017 8:52 am

bakoulis wrote:I just wonder, if is possible to put both SPI & MMFS on the same core and switch between roms with * commands like with romboards on real hardware?
:?:

It could be done, but you would also need to include a ROM manager ROM to allow the inactive one to be disabled (so it doesn't consume memory). Then you would have to educate the user in the use of the ROM manager.

Dave

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Re: Beeb FPGA

Postby adrm » Wed Nov 01, 2017 11:16 pm

Hi all.

Reading this thread was very inspiring and I feel like trying my hand at learning about FPGAs. Starting with the very basics, of course.

Naturally I'd want to run a BBC core on it, as well.

I'm thinking of getting a "mint condition" Altera DE2 Cyclone II (EP2C35) board.

Question 1: Does anyone know if Dave's development for the DE1 will work without modification on this?
Question 2: If modification is required, is this something a rank beginner can be expected to figure out with a bit of hard work, in "reasonable time"? (Yes, I know this is hard to answer)
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Tore

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hoglet
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Re: Beeb FPGA

Postby hoglet » Thu Nov 02, 2017 7:41 am

Hello Tore,
adrm wrote:Question 1: Does anyone know if Dave's development for the DE1 will work without modification on this?

The short answer is no.
adrm wrote:Question 2: If modification is required, is this something a rank beginner can be expected to figure out with a bit of hard work, in "reasonable time"? (Yes, I know this is hard to answer)

Maybe...

You should start by comparing the features in the user manual with the DE1, which is already supported:
- DE1 User Manual
- DE2 User Manual

I've had a quick look and spotted a couple of differences:

1. There are fewer external oscillators on the DE2:
- DE1: 24MHz, 27MHz, 50MHz
- DE2: 27MHz, 50MHz

The Beeb core needs a 32MHz clock, which is currently derived from the 24MHz (using a PLL that multiplies by 4/3). This would need to be changed to use the 50MHz clock (and a PLL that multiplies by 16/25). This should be possible, but it would be worth checking the PLL specs.

2. The DE2 VGA output uses a proper video DAC (a ADV7123) which needs a couple of additional outputs (VGA_BLANK and VGA_SYNC).

You would need to read up on the timing of these signals, and check whether they already exist internally in BeebFPGA.

Even small changes like this can be quite daunting for a beginner!

If it were me, I would install Quartus, check out the project, and try to make the changes before committing to buying the board.

Dave

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bakoulis
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Re: Beeb FPGA

Postby bakoulis » Thu Nov 02, 2017 8:43 am

Why you don't buy a ZX-UNO for only 65 euros and you will have not only Beeb core, but about 20 more home micro cores from a menu of 40 core slots!
http://zxuno.speccy.org/index_e.shtml
2xElectron, 3xBBC B, BBC Master.
2xAcorn A310, A420/1, 2xA3000, 2xA3010, A3020, A4000, A5000.
2xRISC PC, Acorn Pocket Book, Acorn Pocket Book II.

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Re: Beeb FPGA

Postby adrm » Thu Nov 02, 2017 9:59 am

bakoulis wrote:Why you don't buy a ZX-UNO for only 65 euros and you will have not only Beeb core, but about 20 more home micro cores from a menu of 40 core slots!
http://zxuno.speccy.org/index_e.shtml


Thanks, I'll look into the ZX-UNO. I'll read up on them now.
I assume it's a good beginner board to learn FPGA development too?
Edit: Am I correct in assuming that one uses the ISE Design Suite: WebPACK Edition to do development on this board?


If I look at Altera DE1 boards, how concerned should I be about the "RAM issue" (I'd have to buy off eBay)?
Is there any way of identifying these boards?
Last edited by adrm on Thu Nov 02, 2017 10:37 am, edited 1 time in total.
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Tore

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Re: Beeb FPGA

Postby adrm » Thu Nov 02, 2017 10:33 am

hoglet wrote:Hello Tore,

Even small changes like this can be quite daunting for a beginner!

If it were me, I would install Quartus, check out the project, and try to make the changes before committing to buying the board.

Dave


Downloading Quartus now, but I suspect it will be quite a while before I can judge the viability of using a DE2 instead of a DE1 :lol:
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Tore

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Re: Beeb FPGA

Postby hicks » Thu Nov 02, 2017 11:07 am

Maybe I looked at the wrong one, but the prices on the DE2 board don't look all that cheap? Are you wanting it specifically for home computer/bbc recreation? If so, for that price you could get a Replay board. Although it doesn't have a BBC core for it at the moment porting hoglet's (assuming license allows) would be a good project (albeit with quite a large learning curve) and it's made specifically for running multiple arcade and home computer cores.

Other than that if the ZX-Uno linked in a post above is sufficient for the BBC, that'd make a cheaper alternative too.

I'd only get the development board if you want to do other things and find all the little extras on the board useful. Unless I've mixed up boards and it's not as much as I thought.

Note: FPGA Arcade are working on a Replay 2 atm and they hope to have it out by the end of the year, but that's a pretty aggressive schedule that might slip.The first board is still perfectly fine assuming you can get a hold of one. It's what I use for running my Acorn Core on :)

Regarding the "rank beginner" that's a really tough one to answer. However, I went from having done no FPGA development at all, to having a working core (made from scratch) in the space of 2-3 months of evening/weekend learning/mistakes. I've no idea if that's an avg time or not but I've seen others go through a similar process. The initial learning curve is quite steep but not insurmountable.

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Re: Beeb FPGA

Postby adrm » Thu Nov 02, 2017 11:55 am

Hi Hicks.

I was primarily thinking I'd learn about FPGA development, because it looks interesting.
After looking at some examples, I understand the fundamentals and I'm pretty sure I can master those with a bit of time. My worry is that my current lack of knowledge about electronics will make me hit a brick wall, but I'm already looking into that subject, and I have both time and patience :)

My thinking was that looking at / playing with (for example) the work done by Dave would serve as an inspiration when the going gets tough, so being able to load a BBC core on the board I obtain would be a major benefit.
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Tore

vanfanel
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Re: Beeb FPGA

Postby vanfanel » Sun Nov 05, 2017 6:09 pm

@hoglet: Can you please give us precise instructions on how to generate the ROM file on Linux so we can build a MMFS core instead of smart SPI? Azesmbog, on the ZX-UNO forum, is trying to generate it with this command line:

Code: Select all

cat smartmmc.rom.20151002 basic2.rom os12.rom os12.rom |  xxd -c1 -b | cut -c10-17 > rom_image.mif

From those 4 files, one big file is created. Then, from that file the HEX file is made (xxd) and then "cut off".
I believes it is necessary to replace the first ROM, smartmmc.rom, but... with WHAT file? What file should he use instead of smartmmc.rom?

Also, he says -c10-c17 cuts it wrong...

This is the thread where Azesmbog is trying to do it:
http://www.zxuno.com/forum/viewtopic.ph ... 5&start=10

[EDIT] It seems it has worked by doing:

Code: Select all

cat swmmfs.rom basic2.rom os12.rom os12.rom |  xxd -c1 -b | cut -c11-18 > rom_image.mif
Last edited by vanfanel on Sun Nov 05, 2017 6:31 pm, edited 1 time in total.

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Re: Beeb FPGA

Postby hoglet » Sun Nov 05, 2017 6:26 pm

vanfanel wrote:I believes it is necessary to replace the first ROM, smartmmc.rom, but... with WHAT file? What file should he use instead of smartmmc.rom?

Looking at the ZX Uno thread, it seems you are currently using the "sideways ram" version "Model B MMFS SWRAM". This isn't going to work properly on the ZX Uno because you are storing the ROMs in external flash. The SWRAM version needs to be in writable RAM, as it uses the RAM as it's workspace

The file you should be using is called U/MMFS.rom from this archive:
https://github.com/hoglet67/MMFS/releas ... 2_1801.zip

It seems like you have the rest of the process correct though, so give that a try.

Dave

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Re: Beeb FPGA

Postby vanfanel » Sun Nov 05, 2017 11:37 pm

@hoglet: Azesmbog got it to build a core with the MMFS ROM, and the core seems to work.
However, the same exact symptoms of corruption are present with URIDIUM... Any idea on what could be failing now?

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Re: Beeb FPGA

Postby hoglet » Mon Nov 06, 2017 7:39 am

vanfanel wrote:@hoglet: Azesmbog got it to build a core with the MMFS ROM, and the core seems to work.
However, the same exact symptoms of corruption are present with URIDIUM... Any idea on what could be failing now?

Can you post a link to the BEEB.MMB file that is being used for testing?

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Re: Beeb FPGA

Postby vanfanel » Mon Nov 06, 2017 10:19 am

@Hoglet: Or course, we are using this one:
http://stardot.org.uk/files/mmb/higgy_mmbeeb-v1.0.zip

Is yours any different?

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Re: Beeb FPGA

Postby hoglet » Mon Nov 06, 2017 1:18 pm

vanfanel wrote:@Hoglet: Or course, we are using this one:
http://stardot.org.uk/files/mmb/higgy_mmbeeb-v1.0.zip

Is yours any different?

The MMB file is different, but if you look at the .ssd containing Uridium (127) then it's the same. It's Games Disc H1 from the Stairway-to-Hell collection, and it contains 10 other titles (you can see them all if you do *DBOOT 127)

I've done a bit more testing on a real Model B with MMFS 1.36 and I am also seeing some unreliability.

Sometimes it works perfectly, sometimes it seems to hang loading the main game. If you redefine the keys, it seems to hang more often, but I'm not sure that's statistically significant! Also, if you allow the intro music to start, then it doesn't stop properly and the sound in the game is wrong.

So it seems the particular disk conversion of Uridium ("Games Disc H1") that is included in the MMB archive is slightly suspect.

There has been some discussion of this in another thread, and Bill Carr has posted his version:
http://www.stardot.org.uk/forums/viewto ... 71#p184671

This seems to work all the time for me.

Could you give this .ssd a try?

It may be in the end this problem here is a poor disc conversion, rather than any difference between MMFS and SmartSPI.

Dave

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Re: Beeb FPGA

Postby vanfanel » Mon Nov 06, 2017 2:53 pm

@Hoglet: What's the command to load a single SSD in your core, please?
Until now, all I did was running *MENU, and selecting the game (from the list of the games contained in the huge MMB file), but I don't know how to load a single SSD. Maybe it has to be added to the MMB file, but how? Are there GNU/Linux instructions to do so?

The right idea would be to swap the "suspicius" Uridium on the MMB with the sopposedly working version. But I don't know how to do it.

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Re: Beeb FPGA

Postby hoglet » Mon Nov 06, 2017 3:13 pm

vanfanel wrote:@Hoglet: What's the command to load a single SSD in your core, please?
Until now, all I did was running *MENU, and selecting the game (from the list of the games contained in the huge MMB file), but I don't know how to load a single SSD. Maybe it has to be added to the MMB file, but how? Are there GNU/Linux instructions to do so?

For testing, I just picked a blank disk (e.g. 400) and used sweh's mmb_utils package. Here are some instructions.

On Linux:

Code: Select all

mkdir mmb_utils
cd mmb_utils
wget https://sweh.spuddy.org/Beeb/mmb_utils.tar
tar xvf mmb_utils.tar
cd ..
./mmb_utils/dput_ssd.pl -f <path_to_mmb_file> 400 Disc031-UridiumCB.ssd

Replace <path_to_mmb_file> as appropriate.

Then on the Beeb,

Code: Select all

*DBOOT 400

It will be harder to integrate this new version into the STH menu system.

Dave

vanfanel
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Re: Beeb FPGA

Postby vanfanel » Mon Nov 06, 2017 5:17 pm

@Hoglet: thanks a lot for the instructions!
However, it has the same problems... :(

Azesmbog has published a ready-to-use MMB with the new Uridium version here:
http://www.zxuno.com/forum/viewtopic.ph ... 5&start=30
This is the exact link:
http://www.zxuno.com/forum/download/file.php?id=1550

Can you please try it on another Beeb FPGA implementations (different boards)?

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Re: Beeb FPGA

Postby hoglet » Mon Nov 06, 2017 6:39 pm

vanfanel wrote:@Hoglet: thanks a lot for the instructions!
However, it has the same problems... :(

Azesmbog has published a ready-to-use MMB with the new Uridium version here:
http://www.zxuno.com/forum/viewtopic.ph ... 5&start=30
This is the exact link:
http://www.zxuno.com/forum/download/file.php?id=1550

Can you please try it on another Beeb FPGA implementations (different boards)?

I've tried your MMB image with the latest version of Beeb FPGA on the Papilio Duo (but with MMFS 1.36) and Uridium seems to work fine.

ZX Uno forked the core about 2 years ago, so it's possible some change I have made since then is significant.

I'll to a bit of bisection and see if this can find a point in time where Uridium starts failing.

Dave

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Re: Beeb FPGA

Postby vanfanel » Mon Nov 06, 2017 7:21 pm

@Hoglet: I believe Azesmbog on the ZX-UNO thread used the latest sources (with the Speech! problem solved) to do the latest ZX-UNO core, so there shouldn't be any differences regarding the core itself I believe.

EDIT: No, well, Azesmbog mentions some differences (in russian):
"He has a devboard Papilio Duo
as far as I can remember, when I looked at the sources (source) - it has all the ROMs on the external flash-ROM,
in ZXUNO, all ROMs are in BRAM (in the internal ROM).
If Hoglet made a version with internal memory - then it would be easy to port the entire project, and not look for differences, and in which module
something is not working correctly.
And it's so hard for me to port, so I'm just learning"

So, could be BRAM vs flash-ROM the problem? It's the only notable difference, from what I understand.

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Re: Beeb FPGA

Postby hoglet » Mon Nov 06, 2017 8:32 pm

vanfanel wrote:@Hoglet: I believe Azesmbog on the ZX-UNO thread used the latest sources (with the Speech! problem solved) to do the latest ZX-UNO core, so there shouldn't be any differences regarding the core itself I believe.

The biggest functional difference I can see between Zx Uno and Beeb FPGA is in the 6522 model being used:
- ZX Uno is still using V002
- Beeb FPGA is using V005

V002 is very old (more than two years now) and there have been lots of fixes since then. Lots of games depend on subtle behaviours of the 6522. It is a very common source of failures.

As an experiment, I've just downgraded the 6522 in Beeb FPGA on the Papilio to V002 and Uridium now has a random screen corruption that grows slowly over time:
IMG_1130.JPG

Is this the problem you are having?

Unfortunately, it's not quite as simple as replacing the file (with V005 linked above), as the signal timing changed a bit.

This commit should help see the extra registers that needs to be added to the Beeb Core VHDL:
https://github.com/hoglet67/BeebFpga/co ... d7ed9c?w=1

Hope this helps.

Dave


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