Beeb FPGA

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vanfanel
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Re: Beeb FPGA

Postby vanfanel » Tue Nov 07, 2017 9:34 am

@hoglet: That is EXACTLY the problem I see (the same exact screen corruption growing over time).
The problem is I don't know a thing about VHDL, so if signals changed over versions there isn't much I can do.
But at least we know where the problem is. Maybe Azesmbog can come up with something...
I am still willing to donate a ZX-UNO in case you want to give it a go!

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hoglet
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Re: Beeb FPGA

Postby hoglet » Tue Nov 07, 2017 10:54 am

vanfanel wrote:@hoglet: That is EXACTLY the problem I see (the same exact screen corruption growing over time).
The problem is I don't know a thing about VHDL, so if signals changed over versions there isn't much I can do.
But at least we know where the problem is. Maybe Azesmbog can come up with something...
I am still willing to donate a ZX-UNO in case you want to give it a go!

Thanks for your offer to donate a ZX-UNO, but I'm a bit reluctant to take on maintaining the core on yet another platform.

Why not ask antoniovillena for help, he was the person that has done all the work on the Beeb core in ZX-UNO so far?

It's a small change for anyone that knows VHDL.

Dave

vanfanel
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Re: Beeb FPGA

Postby vanfanel » Tue Nov 07, 2017 11:23 am

@Hoglet: Isn't the BBC Micro port the work of Quest?

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bakoulis
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Re: Beeb FPGA

Postby bakoulis » Tue Nov 07, 2017 11:30 am

vanfanel wrote:@Hoglet: Isn't the BBC Micro port the work of Quest?

BBC Micro port is work of Quest.
Antonio Villena is at most a hardware developer, not a software developer.
:?
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hoglet
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Re: Beeb FPGA

Postby hoglet » Tue Nov 07, 2017 12:00 pm

vanfanel wrote:@Hoglet: Isn't the BBC Micro port the work of Quest?

Sorry, yes you are right.

I was confused because I've been looking at a copy of the sources in github:
https://github.com/antoniovillena/zxuno ... s/BBCMicro

All the commits have his name on them (probably due to the incorrect way it has been imported from svn).

vanfanel
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Re: Beeb FPGA

Postby vanfanel » Tue Nov 07, 2017 10:37 pm

@Hoglet: on our ZX-UNO forum thread, Azesmbog has built a core with 6522 V.5, and the graphics issues in Uridium are gone! =D>
BUT sound issues remain: suspended notes during gameplay that change pitch when you shot, etc...
What component could be causing this? We are almost there!

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tricky
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Re: Beeb FPGA

Postby tricky » Wed Nov 08, 2017 6:45 am

I'm sure Hoglet will be along with a better answer, but most software emulators at some point have had a bug latching the channel correctly.

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hoglet
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Re: Beeb FPGA

Postby hoglet » Wed Nov 08, 2017 12:11 pm

vanfanel wrote:@Hoglet: on our ZX-UNO forum thread, Azesmbog has built a core with 6522 V.5, and the graphics issues in Uridium are gone! =D>
BUT sound issues remain: suspended notes during gameplay that change pitch when you shot, etc...
What component could be causing this? We are almost there!

I'm pleased the 6522 V.5 has resolved the graphics issue.

The version of Uridium that's in the Stairway-to-Hell archive (disc 127) has broken sound like this, if you allow the intro tune to start playing. It does this on a real Beeb as well.

Are you definitely using Bill Carr's version of Uridium, not the original one from the archive?
http://www.stardot.org.uk/forums/viewto ... 71#p184671

Also, it might be useful for me to be able to see the latest source code for the ZX-UNO Beeb Core that Azesmbog has modified. Is this on github somewhere?

Dave

vanfanel
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Re: Beeb FPGA

Postby vanfanel » Wed Nov 08, 2017 6:21 pm

@Hoglet: I was using the old version on the BEEB.MMB file, sorry.
Using Bill Carr's version, audio during gameplay is perfect, but tittle screen music sounds distorted at some notes.
Is that supposed to happen?
Azesmbog did a single-game MMB version from Bill Carr's release, available here:
http://www.zxuno.com/forum/download/file.php?id=1550

That is the exact version I am testing with his build now.

I will ask him if he can do a github repo with the ZX-UNO sources.

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hoglet
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Re: Beeb FPGA

Postby hoglet » Wed Nov 08, 2017 6:23 pm

vanfanel wrote:@Hoglet: I was using the old version on the BEEB.MMB file, sorry.
Using Bill Carr's version, audio during gameplay is perfect, but tittle screen music sounds distorted at some notes.
Is that supposed to happen?
Azesmbog did a single-game MMB version from Bill Carr's release, available here:
http://www.zxuno.com/forum/download/file.php?id=1550

That is the exact version I am testing with his build now.

I will ask him if he can do a github repo with the ZX-UNO sources.

Assuming you are using the same SN76489 model that I am, you might just be missing this fix:
https://github.com/hoglet67/BeebFpga/co ... 45d2021387

vanfanel
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Re: Beeb FPGA

Postby vanfanel » Thu Nov 09, 2017 2:54 am

@Hoglet: just in case you don't see it on the ZX-UNO forum, Azesmbog has updated the core again with that fix (and some personal adjustments it seems) and everything sounds great now! =D>
I have asked for the sources so you can finally take a look.

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hoglet
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Re: Beeb FPGA

Postby hoglet » Thu Nov 09, 2017 9:26 am

Glad you got it sorted...

Dave

vanfanel
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Re: Beeb FPGA

Postby vanfanel » Thu Nov 09, 2017 12:27 pm

@hoglet: the sources are now on the ZX-UNO svn here, in case you want to take a look:
http://svn.zxuno.com/svn/zxuno/cores/BBCMicro/test3/

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hoglet
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Re: Beeb FPGA

Postby hoglet » Thu Nov 09, 2017 12:34 pm

vanfanel wrote:@hoglet: the sources are now on the ZX-UNO svn here, in case you want to take a look:
http://svn.zxuno.com/svn/zxuno/cores/BBCMicro/test3/

Just tried building the Xilinx project, it seems a file is missing:
zxuno/cores/BBCMicro/test3/src/sn76489.vhd

Dave

vanfanel
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Re: Beeb FPGA

Postby vanfanel » Thu Nov 09, 2017 2:12 pm

@hoglet: can you build from this file's contents? That's what Azesmbog uploaded himself:
http://www.zxuno.com/forum/download/file.php?id=1555

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hoglet
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Re: Beeb FPGA

Postby hoglet » Thu Nov 09, 2017 2:47 pm

vanfanel wrote:@hoglet: can you build from this file's contents? That's what Azesmbog uploaded himself:
http://www.zxuno.com/forum/download/file.php?id=1555

Yes, I can.

vanfanel
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Re: Beeb FPGA

Postby vanfanel » Fri Nov 10, 2017 12:49 pm

Ah, perfect! Where should we check for important updates on your codebase? For future reference I mean.

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hoglet
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Re: Beeb FPGA

Postby hoglet » Fri Nov 10, 2017 1:23 pm

vanfanel wrote:Ah, perfect! Where should we check for important updates on your codebase? For future reference I mean.

https://github.com/hoglet67/BeebFpga/commits/master

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BigEd
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Re: Beeb FPGA

Postby BigEd » Fri Nov 10, 2017 1:29 pm

(and for those of you using RSS readers:
https://github.com/hoglet67/BeebFpga/co ... aster.atom
)

northernbob
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Re: Beeb FPGA

Postby northernbob » Fri Nov 24, 2017 1:55 pm

just did a search, but cmputer said....no!

https://www.victortrucco.com/Multicore/ ... /BBCModelA

sorry) :wink:

adrm
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Re: Beeb FPGA

Postby adrm » Fri Dec 01, 2017 9:26 pm

Hi, all FPGA experts.
Hoping for a few pointers here.

I finally received my Altera DE2 (Cyclone II) development board and I have enjoyed reading up on VHDL for the last few days.

I have generated a new PLL for the 32MHz clock and (I believe) hooked it up to Mark's code for the DE1. The board appears to be responding to input now, but I haven't gotten to a point where I can try my hand at getting the VGA output on this board working yet.

It would be helpful at this stage if anyone can tell me if the board is supposed to react to KEY(0), and if yes, what it does. Hard reset, maybe?
On my board pressing KEY(0) makes various things happen:
    The HEX displays shows "8888" in the normal state, but KEY(0) can make various other digits appear briefly
    Red LED(0) and (1) are normally on, but KEY(0) can make a few others light up, e.g. 5 and 13

I haven't been able to find a specific reference to KEY(0) in the DE1 code, so I can't deduct is this behaviour indicates a problem(s) or if it's intended behaviour. Maybe there is a .QSF files somewhere that I have overlooked, which would give me a clue about mapping?
-------
Tore

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hoglet
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Re: Beeb FPGA

Postby hoglet » Fri Dec 01, 2017 9:35 pm

Are you using my Altera build, or someone elses? (You mention Mark)

KEY(0) on my DE1 build drives pll_reset:
https://github.com/hoglet67/BeebFpga/bl ... 1.vhd#L331

Which then causes a hard reset:
https://github.com/hoglet67/BeebFpga/bl ... 1.vhd#L349

Dave

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hoglet
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Re: Beeb FPGA

Postby hoglet » Fri Dec 01, 2017 9:48 pm

There's an explanation here of what the switches/keys/LEDs do on the DE1 build:
viewtopic.php?p=125089#p125089

Dave

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Re: Beeb FPGA

Postby adrm » Fri Dec 01, 2017 9:52 pm

Doh!
I was looking at Mike (Stirling) in the code, which somehow got turned into "Mark" :oops:
(I have talked to a surprising number of Marks in Beeb related matters)

Yes, it's your code.
I assume that the behaviour I describe is not intended then, as it seems somewhat random. (The keys on this board, although debounced, seem to be of poor quality, easily giving intermittent contact when pressed. E.g. if you move the button while it's pressed.)

Do you have a recommendation on where to proceed (apart from keep reading up on VHDL) from this point?
Would trying to get the VGA output to work be better, since it's easier to verify when I get it working?

Edit: Thanks for the key/led/switch link. I'd overlooked that.
-------
Tore

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hoglet
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Re: Beeb FPGA

Postby hoglet » Fri Dec 01, 2017 9:59 pm

Do you have PS/2 keyboard connected? Does pressing caps lock toggle one of the LEDs?

Your next step I think should be to try to get a TV or VGA monitor connected.

Is your VHDL code available somewhere?

Dave

adrm
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Re: Beeb FPGA

Postby adrm » Fri Dec 01, 2017 10:15 pm

I have a USB keyboard connected via a USB<->PS2 adapter. Not sure if this causes problems.
Unfortunately, pressing Caps Lock does nothing at this point.


I don't have a place to share my code, as of now.

Apart from changing the device type to EP2C35F672C6 in the Device dialogue, I:

1) Generated a new PLL using the MagaWizard Plugin manager:
component DE2_pll32
PORT
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
end component;

Apart from changing the multiplier/divisor, I have kept it the same as the original PLL (I think)

2) In "bbc_micro_de1.vhd" I made this change:

--------------------------------------------------------
-- Clock Generation
--------------------------------------------------------

-- 32 MHz master clock from 24MHz input clock
-- pll: entity work.pll32
-- port map (
-- areset => pll_reset,
-- inclk0 => CLOCK_24_0,
-- c0 => clock_32,
-- locked => pll_locked
-- );
--TH - 32 MHz master clock from 50MHz input clock. Used for Altera DE2 EP2C35x
pll: entity work.DE2_pll32
port map (
areset => pll_reset,
inclk0 => CLOCK_50,
c0 => clock_32,
locked => pll_locked
);
-------
Tore

adrm
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Re: Beeb FPGA

Postby adrm » Fri Dec 01, 2017 10:29 pm

After another doh! moment, I can report progress.

Having loaded the ROM into the FLASROM, the LED respond to Caps Lock :)
-------
Tore

adrm
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Re: Beeb FPGA

Postby adrm » Fri Dec 01, 2017 10:31 pm

Not unexpectedly, the old LCD monitor with VGA input displays "Out of Timing (Analog)", so this weekend might be a lot of fun
-------
Tore

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hoglet
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Re: Beeb FPGA

Postby hoglet » Fri Dec 01, 2017 10:34 pm

adrm wrote:I have a USB keyboard connected via a USB<->PS2 adapter. Not sure if this causes problems.

That's probably not going to work. Most USB to PS/2 adapters contain very little! Try and find a real PS/2 keyboard.

Have you changed the pin assignment to match the DE2? (In the .QSF file)? This is the most likely source of errors.

Dave

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hoglet
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Re: Beeb FPGA

Postby hoglet » Fri Dec 01, 2017 10:37 pm

adrm wrote:Not unexpectedly, the old LCD monitor with VGA input displays "Out of Timing (Analog)", so this weekend might be a lot of fun

Try all four combinations of SW7 and SW8.

Dave


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