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by hoglet
Mon Dec 04, 2017 10:29 am
Forum: hardware
Topic: Beeb FPGA
Replies: 471
Views: 25520

Re: Beeb FPGA

I enabled Music 5000 (and 65C02 CoPro). Are there any demos readily available for the M5000? Preferably something that can easily be copied onto the SD card. There's a Music 5000 disc here: https://github.com/stardot/b-em/tree/master/discs You need to use a program called MMB Imager to add the .ssd...
by hoglet
Mon Dec 04, 2017 9:30 am
Forum: hardware
Topic: Beeb FPGA
Replies: 471
Views: 25520

Re: Beeb FPGA

If I then, do a hard reset using SW[0] the MODE 7 display gets a lot better, i.e. uprights are the same widths. Sound promising? I've seen something similar. I think this is because there are two possible phases of the 24MHz clock. A suspect it's just moving the problem to different column position...
by hoglet
Sun Dec 03, 2017 9:57 pm
Forum: hardware
Topic: Beeb FPGA
Replies: 471
Views: 25520

Re: Beeb FPGA

If anyone wishes to add this to GITHUB, feel free (I don't have an account). Maybe there is another DE2 newbie out there :) If you could upload the working code to dropbox, I might have a go at adding this in next week. It's always tricker to get a new target working than you might first imagine. L...
by hoglet
Sun Dec 03, 2017 9:13 pm
Forum: hardware
Topic: Beeb FPGA
Replies: 471
Views: 25520

Re: Beeb FPGA

That worked, but now it's complaining about "Card Format?" I assume this means it has problems reading the SD card file system? I believe I formatted it to FAT32 the last time. Seems formatting in Windows 7/10 can be problematic. Try reformatting the card with "SD Formatter" fro...
by hoglet
Sun Dec 03, 2017 8:59 pm
Forum: hardware
Topic: Beeb FPGA
Replies: 471
Views: 25520

Re: Beeb FPGA

BTW, I expect the SD pin misassignments is the reason LED R13 lights up when you press BREAK.
by hoglet
Sun Dec 03, 2017 8:22 pm
Forum: hardware
Topic: Beeb FPGA
Replies: 471
Views: 25520

Re: Beeb FPGA

The mode 7 display looks pretty awful, as Dave found. Apart from the question of "is it worth the effort", I'm wondering if this is fixable, or just a limitation one has to accept? If you compare to the pictures I posted earlier, is what you are seeing the same, or worse? The problem with...
by hoglet
Sun Dec 03, 2017 5:06 pm
Forum: hardware
Topic: M3000 vs M5000
Replies: 44
Views: 1721

Re: M3000 vs M5000

This is great! It looks like Studio3.ssd contains a copy of the extensions to support the Music 3000. A quick disassembly of M.M5 and search for FCFF found the following: 09ED A9 3E LDA #&3E )> 09EF 85 EE STA &EE .n 09F1 8D FF FC STA &FCFF ..| and 0A58 A9 5E LDA #&5E )^ 0A5A 85 EE ST...
by hoglet
Sun Dec 03, 2017 2:29 pm
Forum: hardware
Topic: Beeb FPGA
Replies: 471
Views: 25520

Re: Beeb FPGA

Tore, I've pushed a commit to github that updates the bbc_micro_de1 design to use only the 27MHz clock. https://github.com/hoglet67/BeebFpga/commit/8d403fa7c88a181d0d782883708cbdae02b0b789 Yesterday you reported: I now have MODE 7 working somewhat. The display is quite unstable with a lot of flicker...
by hoglet
Sun Dec 03, 2017 12:54 pm
Forum: hardware
Topic: Beeb FPGA
Replies: 471
Views: 25520

Re: Beeb FPGA

Just one more question for the moment. You say: PLLA: - start with 27MHz and pass this through (the clock control block allows direct use of the clock input) - use m=16,n=1 to get fVCO of 432MHz - use c1 = 18 to get 24MHz Does the underlined part mean that I can use the 27MHz clock BOTH as input to...
by hoglet
Sun Dec 03, 2017 12:06 pm
Forum: hardware
Topic: Beeb FPGA
Replies: 471
Views: 25520

Re: Beeb FPGA

This picture is a very good summary of the structure of the Altera Cyclone II PLL: cyclone_ii_pll_diagram.PNG Source: https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/cyc2/cyc2_cii51007.pdf In my description above, I've ignore k (the VCO post scale counter), which is not...
by hoglet
Sun Dec 03, 2017 11:59 am
Forum: hardware
Topic: Beeb FPGA
Replies: 471
Views: 25520

Re: Beeb FPGA

I guess this confusion can be cleared up with a bit more study, but it connects directly to my failing to understand how your suggestions work. I.e. - use m=16,n=1 to get fVCO of 432MHz ---> Yes, I can set this up - use c1 = 18 to get 24MHz ---> Ehhh? *lots of head scratching* I think this is confu...
by hoglet
Sun Dec 03, 2017 8:03 am
Forum: hardware
Topic: Beeb FPGA
Replies: 471
Views: 25520

Re: Beeb FPGA

[i] Each PLL can be fed by one of four single-ended or two differential clock input pins. For example, PLL 1 can be fed by CLK[3..0] when using a single-ended I/O standard. Does this help us at all? I don't know what a single-ended clock is, but the text seems to indicate that you can share e.g. th...
by hoglet
Sat Dec 02, 2017 11:04 pm
Forum: hardware
Topic: Beeb FPGA
Replies: 471
Views: 25520

Re: Beeb FPGA

OK, so two further alternatives (on paper anyway): ========================================= PLL1: - start with 27MHz, and pass this through - use m=32,n=1 to get fVCO of 864MHz - use c1 = 27 to get 32MHz PLL2: - start with 50MHz - use m=12,n=1 to get fVCO of 600MHz - use c1 = 25 to get 24MHz ======...
by hoglet
Sat Dec 02, 2017 10:48 pm
Forum: hardware
Topic: Beeb FPGA
Replies: 471
Views: 25520

Re: Beeb FPGA

27 * 8 gives fVCO of 216MHz which is too low. It might actually be possible to generate all three clocks using two PLLs as follows: PLL1: - start with 27MHz - use m=32,n=1 to get fVCO of 864MHz - use c1 = 27 to get 32MHz - use c2 = 32 to get 27MHz PLL2: - start with 50MHz - use m=12,n=1 to get fVCO ...
by hoglet
Sat Dec 02, 2017 9:56 pm
Forum: hardware
Topic: Beeb FPGA
Replies: 471
Views: 25520

Re: Beeb FPGA

That's a strange limitation, given that the board has 4 PLLs? It's a design flaw in the DE2 board, rather than the Altera EP2C35. They should have connected each clock to multiple clock input pins, like they did on the DE1. It's worth remembering the Cyclone II architecture was introduced in 2004, ...
by hoglet
Sat Dec 02, 2017 9:44 pm
Forum: hardware
Topic: Beeb FPGA
Replies: 471
Views: 25520

Re: Beeb FPGA

So, what is the approved way to resolve this? E.g. feed CLOCK_50 into multiple SIGNALS and then feed these into the PLLs? I'm not an Altera expert either! But, this does seem to be a rather nasty / fundamental limitation of Cyclone II: https://www.alteraforum.com/forum/showthread.php?t=6399 And it'...
by hoglet
Sat Dec 02, 2017 8:12 pm
Forum: hardware
Topic: Beeb FPGA
Replies: 471
Views: 25520

Re: Beeb FPGA

adrm wrote:I tried switching to the alt scan doubler now that I have a 27MHz clock going. I do get text on the screen, but it's highly unstable.

Agreed, it's like that for me - it depends a lot on the monitor. I probably should take it out.

Dave
by hoglet
Sat Dec 02, 2017 7:56 pm
Forum: hardware
Topic: Beeb FPGA
Replies: 471
Views: 25520

Re: Beeb FPGA

adrm wrote:Where does the 27MHz clock enter into this?

It doesn't, it's only used in the alternative scan doubler.
adrm wrote:I get the impression that only the 32 and 24 MHz clocks feed into it?

Correct.

The issue is you don't have a 24MHz clock going in.

Dave
by hoglet
Sat Dec 02, 2017 5:32 pm
Forum: hardware
Topic: Beeb FPGA
Replies: 471
Views: 25520

Re: Beeb FPGA

#-o I missed the *

Yes, definitely just MODE, not *MODE
by hoglet
Sat Dec 02, 2017 5:01 pm
Forum: hardware
Topic: Beeb FPGA
Replies: 471
Views: 25520

Re: Beeb FPGA

Great progress! The text is blocky (I seem to recall text smoothing being discussed in the thread), and I only get what looks like MODE 6, no matter what position SW0-3 are in. Can you post a photo? (Leave SW 3 down, it's the file system auto-boot selector, which needs to be off) Typing, e.g. "...
by hoglet
Sat Dec 02, 2017 3:46 pm
Forum: hardware
Topic: Beeb FPGA
Replies: 471
Views: 25520

Re: Beeb FPGA

adrm wrote:I did this in "bbc_micro_de1", not in "rgb2vga_scandoubler". I assume that's ok?

Yes, that's the best place.
by hoglet
Sat Dec 02, 2017 3:13 pm
Forum: hardware
Topic: Beeb FPGA
Replies: 471
Views: 25520

Re: Beeb FPGA

Gosh, this is turning out to be quite non-trivial.

As well as VGA_BLANK, and VGA_SYNC, the ADV7123 needs a pixel clock: VGA_CLK.

I suspect without this you will get nothing at all.

So you also need to feed Clock_32 out as VGA_CLK.

Dave
by hoglet
Sat Dec 02, 2017 2:47 pm
Forum: hardware
Topic: Beeb FPGA
Replies: 471
Views: 25520

Re: Beeb FPGA

Unfortunately still no luck. The change I believe I'm seeing is that earlier the screen was showing nothing + the backlight. Now it seems to be showing true black . If that makes any sense? Yes, it does. We'll get there in the end! I've just spotted the DE2 VGA interface has two additional signal, ...
by hoglet
Sat Dec 02, 2017 2:17 pm
Forum: hardware
Topic: Beeb FPGA
Replies: 471
Views: 25520

Re: Beeb FPGA

Try putting SW0 in the up position, then pres Ctrl-F12 (F12 emulates the Beeb's BREAK key). The system should restart in Mode 6, and you might just see something on the screen. Also make sure SW7 is up and SW8 is down, which selects VGA mode with the MIST scan doubler (the one that doesn't use 27MH...
by hoglet
Sat Dec 02, 2017 1:32 pm
Forum: hardware
Topic: Beeb FPGA
Replies: 471
Views: 25520

Re: Beeb FPGA

I can confirm everything you say, except that LEDR(13) is also ON OK, I'm not sure about LED R13 as the DE1 board only had LED's R0-R9 and G0-G7. Let's park that one for now. I think I've spotted an issue with your changes, and it comes down to the missing 24MHz clock. On the DE1 BeebFPGA, the 24MH...
by hoglet
Sat Dec 02, 2017 1:02 pm
Forum: hardware
Topic: Beeb FPGA
Replies: 471
Views: 25520

Re: Beeb FPGA

I've got my DE1 setup on the desk next to me now, so I should be able to check a few more things with you. I will check I can rebuild everything from source, but I need to re-install Quartus (as I have a new dev machine) so that might take an hour. It is possible a bug has crept in, as I don't test ...
by hoglet
Sat Dec 02, 2017 12:21 pm
Forum: hardware
Topic: Beeb FPGA
Replies: 471
Views: 25520

Re: Beeb FPGA

OK, so it seems from the specifications that your monitor should work with a 50Hz/31.25KHz VGA signal. It would really help if you could make your code available somehow. A fork on github would be ideal, but failing that just Zip everything up and upload it to a free account on dropbox. Did you buil...
by hoglet
Sat Dec 02, 2017 7:42 am
Forum: hardware
Topic: Beeb FPGA
Replies: 471
Views: 25520

Re: Beeb FPGA

Pressing <ctrl>-G or Reset (KEY[0]) gives out the expected Beeb sounds from the line out connector. This is a good sign! Is that using a different keyboard, or using the USB-to-PS/2 adapter? I haven't been able to determine if you use the 27MHz clock. It's used for one of the scan doublers (the RGB...
by hoglet
Sat Dec 02, 2017 7:32 am
Forum: hardware
Topic: Tube Detect code
Replies: 14
Views: 314

Re: Tube Detect code

dominicbeesley wrote:Do you have a copy of the datasheet you can share? I couldn't find anything the other day.

This is the copy I've been referring to:
http://archive.6502.org/datasheets/cmd_ ... family.pdf

Dave

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